Cyclone® 10 LP Device Overview

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ID 683879
Date 5/27/2022
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Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview x
Summary of Intel® Cyclone® 10 LP Features Intel® Cyclone® 10 LP Available Options Intel® Cyclone® 10 LP Maximum Resources Intel® Cyclone® 10 LP Package Plan Intel® Cyclone® 10 LP I/O Vertical Migration Logic Elements and Logic Array Blocks Embedded Multipliers Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O Configuration Power Management Document Revision History for Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview

Configuration

Intel® Cyclone® 10 LP devices use SRAM cells to store configuration data. Configuration data is downloaded to the Intel® Cyclone® 10 LP device each time the device powers up.

You can use EPCS or EPCQ (AS x1) flash configuration devices to store configuration data and configure the Intel® Cyclone® 10 LP FPGAs.

  • Intel® Cyclone® 10 LP devices support 1.5 V, 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration schemes.
  • The single-event upset (SEU) mitigation feature detects cyclic redundancy check (CRC) errors automatically during configuration and optionally during user mode1.

Table 5.  Configuration Schemes and Features Supported by Intel® Cyclone® 10 LP Devices
Configuration Scheme Configuration Method Decompression Remote System Upgrade
Active serial (AS) Serial configuration device Yes Yes
Passive serial (PS) External host with flash memory Yes Yes
Download cable Yes —
Fast passive parallel (FPP) External host with flash memory — Yes
JTAG External host with flash memory — —
Download cable — —
Related Information
1 User mode error detection is not supported on 1.0 V core voltage Intel® Cyclone® 10 LP device variants.
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