Intel® Cyclone® 10 LP Device Overview

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ID 683879
Date 5/27/2022
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Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview x
Summary of Intel® Cyclone® 10 LP Features Intel® Cyclone® 10 LP Available Options Intel® Cyclone® 10 LP Maximum Resources Intel® Cyclone® 10 LP Package Plan Intel® Cyclone® 10 LP I/O Vertical Migration Logic Elements and Logic Array Blocks Embedded Multipliers Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O Configuration Power Management Document Revision History for Intel® Cyclone® 10 LP Device Overview
Intel® Cyclone® 10 LP Device Overview
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Summary of Intel® Cyclone® 10 LP Features

Table 1.  Summary of Features for Intel® Cyclone® 10 LP Devices
Feature Description

Technology

  • Low-cost, low-power FPGA fabric
  • 1.0 V and 1.2 V core voltage options
  • Available in commercial, industrial, and automotive temperature grades

Packaging

  • Several package types and footprints:
    • FineLine BGA (FBGA)
    • Enhanced Thin Quad Flat Pack (EQFP)
    • Ultra FineLine BGA (UBGA)
    • Micro FineLine BGA (MBGA)
  • Multiple device densities with pin migration capability
  • RoHS6 compliance

Core architecture
  • Logic elements (LEs)—four-input look-up table (LUT) and register
  • Abundant routing/metal interconnect between all LEs

Internal memory blocks

  • M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable
  • Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM
Embedded multiplier blocks
  • One 18 × 18 or two 9 × 9 multiplier modes, cascadable
  • Complete suite of DSP IPs for algorithmic acceleration

Clock networks

  • Global clocks that drive throughout entire device, feeding all device quadrants
  • Up to 15 dedicated clock pins that can drive up to 20 global clocks

Phase-locked loops (PLLs)

  • Up to four general purpose PLLs
  • Provides robust clock management and synthesis

General-purpose I/Os (GPIOs)

  • Multiple I/O standards support
  • Programmable I/O features
  • True LVDS and emulated LVDS transmitters and receivers
  • On-chip termination (OCT)
SEU mitigation SEU detection during configuration and operation

Configuration

  • Active serial (AS), passive serial (PS), fast passive parallel (FPP)
  • JTAG configuration scheme
  • Configuration data decompression
  • Remote system upgrade
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