Cyclone® 10 LP FPGA

{"limitDisplayedContent":"showAll","collectionRelationTags":{"relations":{"EXCLUDE":["etm-ececc448f2f54f0e87cdf5558856b275","etm-98109f19d4f24b6dad7442422a995aee","etm-f6e0d09943a943d383e81b5f64a3956c","etm-f98414c18285485aa46a8e4c3802bc70"],"AND":["etm-4E407B41-B175-477D-88D4-7F82DD5B00F2"],"Child":["732123"]},"featuredIds":[]},"collectionId":"653137","resultPerPage":50.0,"filters":[{"facetId":"ContentType","type":"ContentType","deprecated":true,"name":"ContentType","position":0},{"facetId":"guidetm0DAA2DF06B4E4AF0BC0754CD12664BE6","field":"stm_10385_en","type":"hierarchical","basePath":"Primary Content Tagging","displayName":"Cyclone® 10 FPGAs","deprecated":false,"rootFilter":"guidetm0DAA2DF06B4E4AF0BC0754CD12664BE6","rootPath":["Primary Content Tagging","Intel® FPGAs","Intel® Programmable Devices","Intel® Cyclone®","Intel® Cyclone® 10 FPGAs"],"position":1},{"facetId":"lastupdated","type":"lastupdated","deprecated":true,"name":"lastupdated","position":2}],"coveoRequestHardLimit":"1000","accessDetailsPagePath":"/content/www/us/en/secure/design/internal/access-details.html","collectionGuids":["etm-4E407B41-B175-477D-88D4-7F82DD5B00F2"],"cardView":false,"ignoreSoftware":true,"sorting":"Newest","defaultImagesPath":"/content/dam/www/public/us/en/images/uatable/default-icons","coveoMaxResults":5000,"coveoSplitSize":0,"fpgaFacetRootPaths":"{\"fpgadevicefamily\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Programmable Devices\"],\"quartusedition\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software\"],\"quartusaddon\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software - Add-ons\"],\"fpgaplatform\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® FPGA Platforms\"]}","newWrapperPageEnabled":true,"descendingSortingForNumericalFacetsName":"[\"Intel® Quartus® Prime Pro Edition\",\"Intel® Quartus® Prime Lite Edition\",\"Intel® Quartus® Prime Standard Edition\",\"Quartus® II Subscription Edition\",\"Quartus® II Web Edition\"]","columnsConfiguration":{"idColumn":false,"dateColumn":false,"versionColumn":false,"contentTypeColumn":false,"columnsMaxSize":0},"dynamicColumnsConfiguration":[{"name":"DynamicColumn_id","type":"id","gtv":"ID","width":60,"selected":true},{"name":"DynamicColumn_date","type":"date","gtv":"Date","width":60,"selected":true},{"name":"DynamicColumn_version","type":"version","gtv":"Version","width":135,"selected":true}],"curatedFilter":[{"title":"Recommended Documents","tags":[{"relationship":"AND","value":"Recommended","id":"etm-a065764d12404422a4010b8396828f63"}]},{"title":"Development Software","tags":[{"relationship":"AND","value":"Development Software","id":"etm-ebfe0f9272ba4af9989d1a08f7494bf0"}]},{"title":"Intellectual Property","tags":[{"relationship":"AND","value":"Intellectual Property","id":"etm-0b7580c08e2b4e9eacf848bf52b528e6"}]},{"title":"Datasheet Group","tags":[{"relationship":"OR","value":"Device Overviews","id":"etm-20ef38132a9243a0826bd1e320b198f9"},{"relationship":"OR","value":"Datasheets","id":"etm-d3b801521ba841da80fdd1a3aae06299"},{"relationship":"OR","value":"Errata","id":"etm-73cf3cc1679b467c94e69dbcdde7fc7f"},{"relationship":"AND","value":"Intel® FPGAs PPCH_L1_98836","id":"etm-DA5A91DF-5E20-493F-9B3E-14E037831DF1"}]}],"updateCollateralMetadataEnabled":true,"relatedAssetsEnable":true,"disableExpandCollapseAll":false,"enableRelatedAssetsOnExpandAll":false,"disableBlueBanner":false,"isICS":false,"isUPE":false}