Thermal Design User Guide: Agilex™ 3 FPGAs and SoCs

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ID 851249
Date 5/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Agilex™ 3 FPGA Thermal Design Guidelines 2. Agilex™ 3 FPGA Mechanical Construction 3. Agilex™ 3 FPGA Compact Thermal Model (CTM) Construction 4. Power and Thermal Calculator (PTC) 5. Thermal Design Process 6. General FPGA Thermal Design Considerations 7. Design Examples 8. Heat Sinks 9. Document Revision History for the Thermal Design User Guide: Agilex™ 3 FPGAs and SoCs A. Agilex™ 3 FPGA Product Keys and Package Drawings
1. Introduction to Agilex™ 3 FPGA Thermal Design Guidelines x
1.1. Thermal Design Requirements 1.2. Thermal Design Flow 1.3. Definitions of Thermal and Power Terms Used in this Document
2. Agilex™ 3 FPGA Mechanical Construction x
2.1. Built-in Temperature Sensors
2.1. Built-in Temperature Sensors x
2.1.1. Agilex™ 3 FPGA Temperature Rating
3. Agilex™ 3 FPGA Compact Thermal Model (CTM) Construction x
3.1. CTM File Format 3.2. Thermal Modeling with the CTM 3.3. CTM Top Temperature, TCASE Virtual Sensor 3.4. Obtaining the CTM
4. Power and Thermal Calculator (PTC) x
4.1. PTC Thermal Tab Parameters 4.2. Thermal Analysis with the PTC 4.3. PTC Thermal Tab Calculation Options 4.4. Thermal Resistances and Low Power Devices 4.5. Sensor Temperatures on the PTC Thermal Tab
5. Thermal Design Process x
5.1. Package Heat Flow Path 5.2. Variables Affecting the Heat Flow Path 5.3. Recommended Thermal Design Method
6. General FPGA Thermal Design Considerations x
6.1. FPGA Power Considerations
6.1. FPGA Power Considerations x
6.1.1. FPGA Maximum Allowed Power Dissipation 6.1.2. Static, Dynamic, and Standby Power 6.1.3. Future-Proofing an FPGA Thermal Design
7. Design Examples x
7.1. Example 1: Find Cooling Solution for Maximum Junction Temperature Limit 7.2. Example 2: Find Available Thermal Margin for Cooling Solution 7.3. Example 3: Find the Ambient Temperature for a Specified Cooling Solution
8. Heat Sinks x
8.1. Attachment Force 8.2. Thermal Interface Material (TIM)
8.2. Thermal Interface Material (TIM) x
8.2.1. Common TIM2 Materials
8.2.1. Common TIM2 Materials x
8.2.1.1. TIM2 Performance Parameters And Challenges 8.2.1.2. Understanding Resistance and Pressure Map Curves
1. Introduction to Agilex™ 3 FPGA Thermal Design Guidelines
2. Agilex™ 3 FPGA Mechanical Construction
3. Agilex™ 3 FPGA Compact Thermal Model (CTM) Construction
4. Power and Thermal Calculator (PTC)
5. Thermal Design Process
6. General FPGA Thermal Design Considerations
7. Design Examples
8. Heat Sinks
9. Document Revision History for the Thermal Design User Guide: Agilex™ 3 FPGAs and SoCs
A. Agilex™ 3 FPGA Product Keys and Package Drawings

5.1. Package Heat Flow Path

Agilex™ 3 devices are lidless, monolithic-die packages. Most are low power devices (<5W), and have significantly different heat sink requirements than other device families. This section describes the differences and the steps necessary to optimally size a thermal solution for Agilex™ 3 packages, using the Power and Thermal Calculator (PTC) and compact thermal model (CTM).

The ΨCA output from the PTC determines how large or efficient the heat sink on the package needs to be. Currently, it is calculated considering all heat generated by the FPGA goes out through the top of the package (through the lid in a lidded package and through the die in a lidless package). These are true for high power packages which have high performance heat sinks on top and generally include forced air flow over the heat sink. The following figure reperesents this condition:

Figure 8. High Power FPGA with Large and Effective Heat Sink

Usually, in systems with low power FPGAs (<5W), the packages might have small (low performance) heat sinks, commonly without any additional airflow. In such cases, only a fraction of the heat generated in the die flows through the top of the package into the heat sink. The remaining heat flows through the substrate of the package and into the PCB. The fraction of heat through to the PCB depends on system design and other boundary conditions. The following figure illustrates this case.

Figure 9. Low Power FPGA with Small Heat Sink

For these system conditions, due to lack of sufficient airflow and/or available space, it is not possible to increase the heat sink performance significantly. In such a scenario, to avoid designing unnecessarily large heat sinks, it is important to size the heat sink while taking into consideration only the amount of heat dissipated through the top of the die and not the amount of heat that can be dissipated through the PCB.

The fraction of heat dissipated through the substrate into the PCB depends on various factors, including:

  • Local ambient temperature inside the system.
  • Air flow above and below the PCB.
  • Heat sink type, material, size, clamping load.
  • Thermal interface material (TIM) between the FPGA and heat sink – TIM material and thickness.
  • Shared heat sink contacting other components that potentially have larger heat loss or higher temperatures.
  • Other high power and high temperature components on the PCB and close to the FPGA that might affect the local PCB temperature.
  • PCB construction, such as the number of layers, copper density in the layers, etc.

The following figure illustrates differences in board layout, thermal solution sizes and flow condition.

Figure 10. Variations in Board Layout, Heat Sink Sizes and Airflow Conditions

Considering the factors discussed above, it has been seen in a small set of systems that the fraction of heat generated in the device dissipating through the top of the device — and if applicable, to the heat sink — ranges between 10% and 90%. Because this is a large range, it is essential that the heat sink be optimally sized to handle the actual amount of heat passing through the top of the device.

Note: The fraction of heat going through to the PCB and the fraction through the top of the die can be estimated accurately only via a system thermal simulation using the CTM provided for that particular Agilex™ 3 device.
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