Thermal Design User Guide: Agilex™ 3 FPGAs and SoCs

ID 851249
Date 5/12/2025
Public
Document Table of Contents

1. Introduction to Agilex™ 3 FPGA Thermal Design Guidelines

Updated for:
Intel® Quartus® Prime Design Suite 25.1
Agilex™ 3 FPGAs are a single-die FPGA packaged in a lidless flip-chip ball grid array (BGA). This package does not have an integrated heat spreader (IHS), and a heat sink, if required, must be directly installed on top of the die with a thermal interface material (TIM) that you provide.

Thermal analysis of this device requires the use of the Power and Thermal Calculator (PTC) and Compact Thermal Model (CTM) for Agilex™ 3 devices. The PTC provides power dissipation and other relevant thermal parameters for use in the analysis. The CTM provides the thermal model for system thermal simulations. Both the PTC and CTM are available for download; contact your Altera Field Application Engineer (FAE) for more information.

Agilex™ 3 device packages have powers that range from low (~1W) to medium (~5W). The thermal design process differs based on the power dissipation and system construction. This user guide describes the process of designing thermal solutions for Agilex™ 3 packages.