AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

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ID 848984
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Preparing LiteRT Inference Model 3. Generating Nios® V Processor System 4. Generating Arm Processor System 5. Programming and Running 6. Nios® V Processor with TinyML Design Example 7. Appendix 8. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
1. Overview x
1.1. Requirements
2. Preparing LiteRT Inference Model x
2.1. Defining the Problem 2.2. Gathering and Preparing Sample Data 2.3. Building TensorFlow Model 2.4. Preparing the LiteRT Model 2.5. Preparing Binaries for C/C++
2.2. Gathering and Preparing Sample Data x
2.2.1. Preparing Dataset 2.2.2. Preprocessing Dataset
2.3. Building TensorFlow Model x
2.3.1. Constructing Model Architecture 2.3.2. Configuring Model 2.3.3. Training Model 2.3.4. Evaluating the Model 2.3.5. Saving and Loading Model
2.4. Preparing the LiteRT Model x
2.4.1. Converting into LiteRT Model 2.4.2. Saving the LiteRT Model 2.4.3. Analyzing the LiteRT Model 2.4.4. Loading a LiteRT Interpreter 2.4.5. Evaluating the LiteRT Model
2.5. Preparing Binaries for C/C++ x
2.5.1. Converting LiteRT to a C Array 2.5.2. Preparing a Header File for LiteRT C Array 2.5.3. Preparing Supporting Header File for LiteRT C Array 2.5.4. Preparing Main Function to Run TinyML 2.5.5. Converting MNIST Sample into C Array
3. Generating Nios® V Processor System x
3.1. Building Hardware Design in Platform Designer 3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs x
3.2.1. Creating a Board Support Package 3.2.2. Building LiteRT for Microcontroller Static Library 3.2.3. Creating an Application Project File 3.2.4. Building the LiteRT TinyML Application
4. Generating Arm Processor System x
4.1. GHRD Hardware Design 4.2. Building the Software Design
4.2. Building the Software Design x
4.2.1. Arm-Trusted-Firmware 4.2.2. Building LiteRT for Microcontrollers Static Library 4.2.3. Zephyr OS Environment Setup 4.2.4. Building the LiteRT TinyML Application
4.2.1. Arm-Trusted-Firmware x
4.2.1.1. Booting from QSPI Flash 4.2.1.2. Running through Ashling* RiscFree* IDE for Altera® FPGAs Debugger
5. Programming and Running x
5.1. Nios® V Processor System 5.2. Arm HPS Processor System
5.2. Arm HPS Processor System x
5.2.1. Booting from QSPI 5.2.2. Booting via the Debugger
6. Nios® V Processor with TinyML Design Example x
6.1. Finding Nios® V Processor with TinyML Design Example
7. Appendix x
7.1. main.cc for Nios V Processor 7.2. main.cc for Arm HPS Processor
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Nios® V Processor with TinyML Design Example
7. Appendix
8. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

2.3.3. Training Model

Feed the training data into the model in batches and validate the model on the validation set after each epoch to monitor performance. Using the Matplotlib library, you can display the training and validation accuracy in a line graph.

# Train and Validate the Model
epochs = 10
history = model.fit(x_train, y_train, epochs=epochs, batch_size=128, validation_data = (x_test, y_test), verbose=1)

# Display the Training Progress
def summary_history(history):
  plt.figure(figsize = (10,6))
  plt.plot(history.history['accuracy'], color = 'blue', label = 'train')
  plt.plot(history.history['val_accuracy'], color = 'red', label = 'val')
  plt.legend()
  plt.title('Accuracy')
  plt.show()

summary_history(history)
Figure 3. Training and Validation Logs
Figure 4. Training and Validation Accuracy per Epoches
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