AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

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ID 848984
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Preparing LiteRT Inference Model 3. Generating Nios® V Processor System 4. Generating Arm Processor System 5. Programming and Running 6. Appendix 7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
1. Overview x
1.1. Requirements
2. Preparing LiteRT Inference Model x
2.1. Defining the Problem 2.2. Gathering and Preparing Sample Data 2.3. Building TensorFlow Model 2.4. Preparing the LiteRT Model 2.5. Preparing Binaries for C/C++
2.2. Gathering and Preparing Sample Data x
2.2.1. Preparing Dataset 2.2.2. Preprocessing Dataset
2.3. Building TensorFlow Model x
2.3.1. Constructing Model Architecture 2.3.2. Configuring Model 2.3.3. Training Model 2.3.4. Evaluating the Model 2.3.5. Saving and Loading Model
2.4. Preparing the LiteRT Model x
2.4.1. Converting into LiteRT Model 2.4.2. Saving the LiteRT Model 2.4.3. Analyzing the LiteRT Model 2.4.4. Loading a LiteRT Interpreter 2.4.5. Evaluating the LiteRT Model
2.5. Preparing Binaries for C/C++ x
2.5.1. Converting LiteRT to a C Array 2.5.2. Preparing a Header File for LiteRT C Array 2.5.3. Preparing Supporting Header File for LiteRT C Array 2.5.4. Preparing Main Function to Run TinyML 2.5.5. Converting MNIST Sample into C Array
3. Generating Nios® V Processor System x
3.1. Building Hardware Design in Platform Designer 3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs x
3.2.1. Creating a Board Support Package 3.2.2. Building LiteRT for Microcontroller Static Library 3.2.3. Creating an Application Project File 3.2.4. Building the LiteRT TinyML Application
4. Generating Arm Processor System x
4.1. GHRD Hardware Design 4.2. Building the Software Design
4.2. Building the Software Design x
4.2.1. Arm-Trusted-Firmware 4.2.2. Building LiteRT for Microcontrollers Static Library 4.2.3. Zephyr OS Environment Setup 4.2.4. Building the LiteRT TinyML Application
4.2.1. Arm-Trusted-Firmware x
4.2.1.1. Booting from QSPI Flash 4.2.1.2. Running through Ashling* RiscFree* IDE for Altera® FPGAs Debugger
5. Programming and Running x
5.1. Nios® V Processor System 5.2. Arm HPS Processor System
5.2. Arm HPS Processor System x
5.2.1. Booting from QSPI 5.2.2. Booting via the Debugger
6. Appendix x
6.1. main.cc for Nios V Processor 6.2. main.cc for Arm HPS Processor
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Appendix
7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

4.1. GHRD Hardware Design

Altera provides several GHRDs based on the FPGA SoC devices. This includes Stratix® 10, Agilex™ 7, and Agilex™ 5. The GHRD contains the following items:

  • Arm* Cortex* processors
  • Secure Digital/Embedded Multimedia Card (SD/eMMC) host controller
  • Ethernet Media Access Controller (EMAC)
  • USB UART
  • HPS External Memory Interface (EMIF)
  • FPGA peripherals, which can be customized based on the design needs.

A generic system-level design of Altera GHRD can be seen in the following figure. For more information, refer to the Hard Processor System Technical Reference Manual for specific Altera FPGA SoC devices.

Figure 18.  Altera GHRD System Level Design

Refer to the following steps to prepare the GHRD:

  1. Identify the target Altera FPGA SoC devices. This example uses the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
  2. Install the appropriate Quartus® Prime Pro Edition software version. This example uses Quartus® Prime Pro Edition software version 24.3.
  3. Start with the toolchain setup:
    $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel

    /gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
$ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
$ rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
$ export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
$ export ARCH=arm64
$ export CROSS_COMPILE=aarch64-none-linux-gnu-
$ export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.3/quartus/
$ export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH
  4. Follow the steps below to build the GHRD for Agilex™ 5 SoC:
    $ mkdir tinyml_dev && cd tinyml_dev
$ export TOP_FOLDER=$(pwd)
$ git clone -b QPDS24.3_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
$ mv ghrd-socfpga/agilex5_soc_devkit_ghrd .
$ rm -rf ghrd-socfpga
$ cd agilex5_soc_devkit_ghrd
$ make config
$ make DEVICE=A5ED065BB32AE6SR0 HPS_EMIF_MEM_CLK_FREQ_MHZ=800 HPS_EMIF_REF_CLK_FREQ_MHZ=100 generate_from_tcl
$ make all

These steps generate the bitstream file that programs the board. You can start programming the board once the ATF bootloader is generated.

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