AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
ID
848984
Date
9/29/2025
Public
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Nios® V Processor with TinyML Design Example
7. Appendix
8. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
2.2.2. Preprocessing Dataset
Perform data preprocessing by reshaping, normalizing, and encoding the dataset.
# Reshape the data into a 4D Array x_train = x_train.reshape(x_train.shape[0], rows, cols, 1) x_test = x_test.reshape(x_test.shape[0], rows, cols, 1) input_shape = (rows,cols,1) # Set type as float32 and normalize the values to [0,1] x_train = x_train.astype('float32') x_test = x_test.astype('float32') x_train = x_train / 255.0 x_test = x_test / 255.0 # Transform labels to one hot encoding y_train = tf.keras.utils.to_categorical(y_train, 10) y_test = tf.keras.utils.to_categorical(y_test, 10)