AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
ID
848984
Date
9/29/2025
Public
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Nios® V Processor with TinyML Design Example
7. Appendix
8. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
3. Generating Nios® V Processor System
The general implementation of the Nios® V processor system has two parts: hardware design and software design. The hardware design, which comprises the Nios V processor and peripherals, is developed using the Quartus® Prime software.
Developing a Nios® V processor application requires a software design that complements the processor hardware design. You can develop a Nios® V processor software design using Ashling* RiscFree* IDE for Altera® FPGAs.