Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

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ID 848793
Date 8/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package M12A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B18B 2.3.5. Package B23C
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 3 C-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. LPDDR4 Interfaces
3.8. Power x
3.8.1. Power Rails for Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 3 Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

2.3.3. Package B18A

Figure 5. Consideration Details

The B18A package is available with Device Specification of option Y and Z. Transceiver and HPS are not supported in this package. Support for EMIF and MIPI depends on the Device Specification of the selected device. The considerations taken when migrating between this package depends on which device and Device Specification you are migrating to. The B18A package is available with the same HVIO and HSIO count. There is an output pin utilization limit consideration required for HVIO pin.

Refer to the following examples to understand the areas that require consideration when planning for migration within the B18A package.

Examples:
  • If you are migrating within Device Specification Z of A3C065 to A3C135 devices, neither device supports HPS, EMIF, or MIPI. The resource count for HVIO and HSIO are the same. This is categorized as Vertical Migration which has no impact on board design guidelines.
  • If you are migrating from Device Specification Z of A3C065 to Device Specification Y of A3C135 devices, then you are migrating from devices with unsupported EMIF and MIPI features to supported devices.
  • If you are migrating from A3C065 devices to A3C135 device, then you are migrating from devices that do not have any output pin utilization limit on the HVIO bank to devices that do have an output pin utilization limit. This requirement applicable for both Y and Z Device Specification of this package.

The following table summarizes the areas that require consideration when planning migration within the B18A package. Refer to Functional Area for more details on each area.

Table 5.  B18A Package Consideration Requirement
Area Consideration Requirement
I/O Yes, refer to the I/O section for more details.
LVDS SERDES Yes, refer to the LVDS SERDES section for more details.
Configuration No
EMIF Yes, refer to the External Memory Interface section for more details.
MIPI Yes, refer to the MIPI D-PHY section for more details.
HPS NA
Transceiver NA
Power No
Sensor Yes, refer to the Sensor section for more details.
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