Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series
ID
848793
Date
8/07/2025
Public
1. Introduction
This application note provides migration guidelines for Agilex™ 3 C-Series devices. The guidelines covers various device features to help you plan your Quartus® Prime software and board design up front to ensure seamless migration between devices within the same package.
Figure 1. Agilex™ 3 C-Series Device

Note: Refer to the Agilex™ 3 FPGAs and SoCs Device Overview for Ordering Part Number (OPN) Structure details.
Figure 2. Package Options, Migrations, and I/O Pins
- The arrows indicate the package migration paths. The shades represent the devices included in each path.
- Migration path shown includes both vertical and conditional migration scenario. Refer to Migration Scope for more details.
- To achieve full I/O1 migration across devices in the same migration path, restrict I/Os and transceivers utilization to match the device with the lowest I/O and transceiver counts.
1
- HSIO – High-speed I/O
- HVIO – High voltage I/O
- LVDS – Low voltage differential signaling channels