Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

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ID 848793
Date 8/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package M12A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B18B 2.3.5. Package B23C
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 3 C-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. LPDDR4 Interfaces
3.8. Power x
3.8.1. Power Rails for Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 3 Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

3.2. LVDS SERDES

The LVDS SERDES IP supports different data rates across speed grades within Agilex™ 3 Device Specification W, Y and Z. If you are planning to migrate your design across device, you need to pre-plan your design by selecting the data rate range supported by both devices.

For example,
  • -6 Speed Grade supported Fmax = 1250 Mbps
  • -7 Speed Grade supported Fmax = 1000 Mbps

If you migrate your design from -6 speed grade to -7 speed grade devices, you need to limit the data rate by 1000 Mbps or lower than -7 speed grade supported Fmax.

The LVDS SERDES IP supports multiple I/O standards, features, and data rates in Agilex™ 3 devices. There is no change needed when Quartus® Prime design migration happens between Agilex™ 3 devices if the supported I/O standards, features, and data rates within Agilex™ 3 devices are identical.

Refer to the LVDS SERDES User Guide: Agilex™ 3 FPGAs and SoCs for more information regarding the I/O standards and features for Agilex™ 3 devices.

Refer to the Agilex™ 3 FPGAs and SoCs Device Data Sheet for more information regarding supported data rate for Agilex™ 3 devices.

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