Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series
ID
848793
Date
8/07/2025
Public
3.4.2.1. LPDDR4 Interfaces
The following table shows the maximum number of LPDDR4 interfaces per device.
Package | Number of HSIO Banks | HSIO Pins Count | Avalon® Streaming Interface x16 Support | LPDDR4 x32 | LPDDR4 x16 |
---|---|---|---|---|---|
B18A | 1 | 48 | No | – | 1 |
Yes | – | – | |||
M12A | 1 | 72 | No | – | 1 |
Yes | – | – | |||
B18B | 1 | 96 | No | 1 | 1 |
Yes | – | 1 | |||
B23C | 2 | 144 | No | 1 | 2 |
Yes | – | 2 | |||
M16A | 2 | 192 | No | 2 | 2 |
Yes | 1 | 2 |
Note: These values correspond to Fabric EMIF instances.