Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

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ID 848793
Date 8/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package M12A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B18B 2.3.5. Package B23C
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 3 C-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. LPDDR4 Interfaces
3.8. Power x
3.8.1. Power Rails for Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 3 Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

3.1.2. HVIO

Direct migration using identical pin planning and location is supported when migrating between devices within package M12A, M16A, B18B, and B23C because all devices within each of these packages have the same HVIO location availability. There is no change required to the VCCIO_HVIO supply of these HVIO banks during migration.

For the B18A package, there is a HVIO output pin utilization limit on A3C100 and A3C135 devices. Migration between B18A package should consider the achievable amount of output pin utilization limit based on A3C100 and A3C135 devices.

If you are migrating from A3C100 and A3C135 devices to A3C025, A3C050, and A3C065 devices, you can reuse the same I/O planning and location.

Consideration must be taken when you are migrating from A3C025, A3C050, and A3C065 devices to A3C100 and A3C135 devices. Plan your design upfront in A3C025, A3C050, and A3C065 devices to ensure you only utilize the lesser output pins in the HVIO bank based on the achievable output pin count in A3C100 and A3C135 devices. There is no change required to the VCCIO_HVIO supply of these HVIO banks during migration.

Make use of the HVIO Overshoot Estimator to plan your HVIO pin utilization.

Refer to the Agilex™ 3 Pin-Out Files for more information regarding the VCCIO_HVIO pin location for Agilex™ 3 devices.

Refer to the General Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs for more information regarding HVIO bank feature, design guideline and HVIO Overshoot Estimator for Agilex™ 3 Device.

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