Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

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ID 848793
Date 8/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package M12A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B18B 2.3.5. Package B23C
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 3 C-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. LPDDR4 Interfaces
3.8. Power x
3.8.1. Power Rails for Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 3 Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 3 FPGAs and SoCs C-Series

3.4.3. External Memory Interface Migration Consideration

When planning for device migration, ensure the Device Specification selected supports EMIF.

Refer to the migration path for Agilex™ 3 devices in the Considerations for Migration Planning section.

The maximum number of EMIF interfaces supported when migrating to device within the package are the same because all devices within each of these packages have the same number of HSIO counts.

Consideration must be taken when you are migrating to/from devices with Device Specification Z since these devices do not support EMIF. Plan your board design upfront if you are planning to support EMIF with Device Specification W and Y devices in future migration.

Refer to the following documents for more information regarding External Memory Interface for Agilex™ 3 devices:
  • Agilex™ 3 Device Pin-Out Files
  • Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
  • External Memory Interface Spec Estimator Tool
  • External Memory Interfaces (EMIF) IP User Guide: Agilex™ 3 FPGA and SoCs
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