Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

7.7.1. PLL Output Configuration for Each Speed Grade

The following table represents the parameters that can programmed into the clock manager registers to meet the indicated Agilex™ 3 device speed grades.

Table 320.  PLL Output Configuration for Each Speed Grade
Clock Speed Grade

–6

(0.78 V)

–7

(0.75 V)

Ref Clock 25/100/125 25/100/125
pll_main_vco 3200 3200
pll_main_c0 800 800
pll_main_c1 800 800
pll_main_c2 533.33 533.33
pll_main_c3 400 400
 
pll_peri_vco 3000 3000
pll_peri_c0 600 600
pll_peri_c1 600 600
pll_peri_c2 24 24
pll_peri_c3 500 500
 
mpu_free_clk 533.33 533.33
core0_clk 800 800
core1_clk 800 800
Source for each clock
dsu_clk pll_main_c2 pll_main_c2
core0_clk pll_peri_c1 pll_peri_c1
core1_clk pll_peri_c1 pll_peri_c1