Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

3. Micro Processor Unit (MPU)

The Micro Processor Unit (MPU) consists of multi-core Armv8.2-A architecture central processing units (CPUs), including a dual-core Arm* Cortex* -A55 processor. These CPUs operate with the DynamIQ Shared Unit (DSU) to create a two-core cluster that allows the CPUs to run asynchronously to each other. Each CPU has a level 1 (L1) memory system and a private integrated level 2 (L2) cache. The DSU comprises a level 3 (L3) memory system, control logic, and external interfaces. Advanced functions such as floating-point operations and cryptographic extensions are supported.