Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

4.4.4.5.1. Pipeline and Timing

The RAM controller is a pipelined design, where:
  • The Write path (full width) pipeline is two stages deep; therefore providing a two clock latency.
  • The Write path (subword access) pipeline is three stages deep to account for the read-modify-write.
  • The Read path pipeline is four stages deep for RAM.