GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

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ID 848477
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate and Compile (MAC+PCS) Design Example 6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example 7. Simulate and Compile SyncE Design Example 8. Simulate and Compile PTP1588 Design Example 9. Troubleshoot and Diagnose Issues 10. Appendix A: Functional Description 11. Appendix B: Configuration Registers 12. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex 3 FPGAs and SoCs
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex® 3 Ethernet Portfolio and Target Applications 1.5. Agilex® 3 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex® 3 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization 1.5.4. Round-Trip Latency
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections 4.1.2. Implement Clock Connections to MAC Asynchronous Operation 4.1.3. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.4. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate and Compile (MAC+PCS) Design Example x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
7. Simulate and Compile SyncE Design Example x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow 10GE Ethernet with SyncE 7.3.2. Simulator Output
8. Simulate and Compile PTP1588 Design Example x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
9. Troubleshoot and Diagnose Issues x
9.1. Enable Diagnostic Lookback Modes 9.2. Troubleshoot the Reset Sequence
9.1. Enable Diagnostic Lookback Modes x
9.1.1. Internal Serial Loopback 9.1.2. Enable MAC Loopback 9.1.3. Enable PCS Loopback 9.1.4. Enable External Loopback 9.1.5. Packet Client Loopback
9.2. Troubleshoot the Reset Sequence x
9.2.1. Debug the Power Up Reset Sequence 9.2.2. Debug the TX Reset Entry Sequence 9.2.3. Debug the TX Reset Exit Sequence 9.2.4. Debug the RX Reset Entry Sequence 9.2.5. Debug the RX Reset Exit Sequence 9.2.6. Debug the Auto Recovery Reset Sequence
10. Appendix A: Functional Description x
10.1. Datapath Description 10.2. GTS Ethernet Intel® FPGA Hard IP MAC 10.3. PCS, OTN, and FlexE Modes 10.4. Precision Time Protocol Interface
10.2. GTS Ethernet Intel® FPGA Hard IP MAC x
10.2.1. MAC TX Datapath 10.2.2. MAC RX Datapath 10.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 10.2.4. Link Fault Signaling 10.2.5. Order of Ethernet Transmission:
10.2.1. MAC TX Datapath x
10.2.1.1. Insert TX Preamble, Start, and SFD 10.2.1.2. Insert Source Address 10.2.1.3. Process Length/Type Field 10.2.1.4. Pad the Client Frame 10.2.1.5. Insert Frame Check Sequence (CRC-32) 10.2.1.6. Generate and Insert Inter-Packet Gap
10.2.2. MAC RX Datapath x
10.2.2.1. Process RX Preamble 10.2.2.2. Check RX Strict SFD 10.2.2.3. Check RX FCS 10.2.2.4. Handle RX Malformed Packet 10.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames 10.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 10.2.2.7. Inter-Packet Gap
10.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
10.2.3.1. Conditions Triggering XOFF Frame Transmission 10.2.3.2. Conditions Triggering XON Frame Transmission 10.2.3.3. Pause Control and Generation Interface 10.2.3.4. Pause Control Frame Filtering
10.3. PCS, OTN, and FlexE Modes x
10.3.1. PCS Mode 10.3.2. OTN Mode 10.3.3. FlexE Mode
10.4. Precision Time Protocol Interface x
10.4.1. Features 10.4.2. PTP User Flow 10.4.3. Make PTP UI Adjustments 10.4.4. Reference Time Interval
10.4.2. PTP User Flow x
10.4.2.1. PTP TX User Flow 10.4.2.2. PTP RX User Flow
10.4.3. Make PTP UI Adjustments x
10.4.3.1. Adjust TX UI 10.4.3.2. Adjust RX UI
11. Appendix B: Configuration Registers x
11.1. Ethernet Avalon® Memory-Mapped Interface Address Space 11.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Troubleshoot and Diagnose Issues
10. Appendix A: Functional Description
11. Appendix B: Configuration Registers
12. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex 3 FPGAs and SoCs

11.2. Packet Client Registers

You can customize the GTS Ethernet Intel® FPGA Hard IP hardware design example by programming the packet client registers for IP variants. These registers are not included in the Agilex™ 3 Ethernet Intel® FPGA Hard IP Register Map.

To access the packet client registers, the address value is calculated using both the base and offset address. For example, to access hw_test_rom_addr register, add offset address 0x08 to the packet client register base address 0x100000, which results in 0x100008.

Table 57.  Packet Client Registers for MAC Avalon® ST Interface
Note: All address offsets are specified in the byte address format.
Address Name Bit Offset Default Value Access Description
0x00 hw_pc_ctrl 0 1'b0 RW Start and stop of the TX packet generation.
  • 0: Stop packet generator
  • 1: Start packet generator
2 1'b0 RW Packet transmission mode.
  • 0: One time mode
  • 1: Continuous mode

When you switch from continuous to one time mode, you must set hw_pc_ctrl[0] to 1 to ensure the pending packet transmission is completed.

4 1'b0 RW Packet client loopback.
  • 0: Packet generator data path: Data flow from packet client to TX data path
  • 1: Loopback client data path: RX MAC Avalon Streaming loopback to TX MAC Avalon Streaming Client Interface
6 1'b0 RW The snapshot status for all statistics counter registers.
  • 0: No snapshot
  • 1: Snapshot available
7 1'b0 RW The clear status of the snapshot registers.
  • 0: Do not clear the internal registers
  • 1: Clear the internal registers
8 1'b0 RW The EOP of TX packet and clears the counters.
0x0C Loopback_FIFO_status [0] 0 RW Loopback FIFO write full error
[1] 0 RW Loopback FIFO read empty error
[15:2] 14'h0000 RW Reserved. Default 0s
0x1C cfg_rom_pkt_gap [4:0] 0 RW

Gap insertion between the packets. avst: min gap = 0; max gap = 31

[31:5] 0 RW Reserved. Default 0s.
0x04 hw_test_loop_cnt [15:0] 16'd1 RW Indicates the number of times the ROM packet data are sent.
0x08 hw_test_rom_addr [15:0] 16'd0 RW ROM packet data start address
[31:16] 16'd0 RW ROM packet data end address
0x10 Latency Reg [7:0] 8'h00 RO Latency Value in terms of o_clk_pll
[30:8] 23'd0 RO Reserved
[31] 0 RW Latency enable bit (self- clearing)
0x14 cfg_rom_da_addr [31:0] 0 RW Destination address LSB 32 bits
0x18 Cfg_rom_da_adr_h [15:0] 0 RW Destination address LSB 16 bits
[16] 0 RW 16th bit = 1/0 to enable/disable DA insertion
[31:17] 0 RW Reserved. Default 0s
0x20 stat_tx_sop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the TX start-of-packet (SOP) counter
0x24 stat_tx_sop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the TX start-of-packet (SOP) counter
0x28 stat_tx_eop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the TX end-of-packet (EOP) counter
0x2C stat_tx_eop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the TX end-of-packet (EOP) counter
0x30 stat_tx_err_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the TX error counter
0x34 stat_tx_err_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the TX error counter
0x38 stat_rx_sop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the RX start-of-packet (SOP) counter
0x3C stat_rx_sop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the RX start-of-packet (SOP) counter
0x40 stat_rx_eop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the RX end-of-packet (EOP) counter
0x44 stat_rx_eop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the RX end-of-packet (EOP) counter
0x48 stat_rx_err_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the RX error counter
0x4C stat_rx_err_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the RX error counter
Table 58.  Packet Client Registers for PCS, OTN, and FlexE Interface
Note: All address offsets are specified in the byte address format.
Address Name Bit Offset Default Value Access Description
0x10 cfg_start_pkt_gen 0 1'b0 RW Start and stop TX packet generator.
  • 0: Stop packet generator.
  • 1: Start packet generator.
0x58 cfg_clear_counters 0 1'b0 RW When set, clears packet generator counters.
0x18 stat_tx_sop_cnt [31:0] 32'b0 RO Lower 32-bits of the TX start-of-packet (SOP) counter
0x1C stat_tx_sop_cnt [31:0] 32'b0 RO Upper 32-bits of the TX start-of packet (SOP) counter
0x20 stat_tx_eop_cnt [31:0] 32'b0 RO Lower 32-bits of the TX end-of-packet (EOP) counter
0x24 stat_tx_eop_cnt [31:0] 32'b0 RO Upper 32-bits of the TX end-of-packet (EOP) counter
0x30 stat_rx_sop_cnt [31:0] 32'b0 RO Lower 32-bits of the RX start-of-packet (SOP) counter
0x34 stat_rx_sop_cnt [31:0] 32'b0 RO Upper 32-bits of the RX start-of-packet (SOP) counter
0x38 stat_rx_eop_cnt [31:0] 32'b0 RO Lower 32-bits of the RX end-of-packet (EOP) counter
0x3C stat_rx_eop_cnt [31:0] 32'b0 RO Upper 32-bits of the RX end-of-packet (EOP) counter
0x50 stat_rx_err_cnt [31:0] 32'b0 RO Lower 32-bits of the RX error status
0x54 stat_rx_err_cnt [31:0] 32'b0 RO Upper 32-bits of the RX error status
Level Two Title