GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

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ID 848477
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Intel® FPGA Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application 5. Simulate and Compile (MAC+PCS) Design Example 6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example 7. Simulate and Compile SyncE Design Example 8. Simulate and Compile PTP1588 Design Example 9. Troubleshoot and Diagnose Issues 10. Appendix A: Functional Description 11. Appendix B: Configuration Registers 12. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex 3 FPGAs and SoCs
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex® 3 Ethernet Portfolio and Target Applications 1.5. Agilex® 3 Ethernet Hard IP Features 1.6. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.5. Agilex® 3 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization 1.5.4. Round-Trip Latency
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections 4.1.2. Implement Clock Connections to MAC Asynchronous Operation 4.1.3. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.4. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP
4.2.2. Connect the GTS Reset Sequencer Intel® FPGA IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate and Compile (MAC+PCS) Design Example x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
7. Simulate and Compile SyncE Design Example x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow 10GE Ethernet with SyncE 7.3.2. Simulator Output
8. Simulate and Compile PTP1588 Design Example x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
9. Troubleshoot and Diagnose Issues x
9.1. Enable Diagnostic Lookback Modes 9.2. Troubleshoot the Reset Sequence
9.1. Enable Diagnostic Lookback Modes x
9.1.1. Internal Serial Loopback 9.1.2. Enable MAC Loopback 9.1.3. Enable PCS Loopback 9.1.4. Enable External Loopback 9.1.5. Packet Client Loopback
9.2. Troubleshoot the Reset Sequence x
9.2.1. Debug the Power Up Reset Sequence 9.2.2. Debug the TX Reset Entry Sequence 9.2.3. Debug the TX Reset Exit Sequence 9.2.4. Debug the RX Reset Entry Sequence 9.2.5. Debug the RX Reset Exit Sequence 9.2.6. Debug the Auto Recovery Reset Sequence
10. Appendix A: Functional Description x
10.1. Datapath Description 10.2. GTS Ethernet Intel® FPGA Hard IP MAC 10.3. PCS, OTN, and FlexE Modes 10.4. Precision Time Protocol Interface
10.2. GTS Ethernet Intel® FPGA Hard IP MAC x
10.2.1. MAC TX Datapath 10.2.2. MAC RX Datapath 10.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 10.2.4. Link Fault Signaling 10.2.5. Order of Ethernet Transmission:
10.2.1. MAC TX Datapath x
10.2.1.1. Insert TX Preamble, Start, and SFD 10.2.1.2. Insert Source Address 10.2.1.3. Process Length/Type Field 10.2.1.4. Pad the Client Frame 10.2.1.5. Insert Frame Check Sequence (CRC-32) 10.2.1.6. Generate and Insert Inter-Packet Gap
10.2.2. MAC RX Datapath x
10.2.2.1. Process RX Preamble 10.2.2.2. Check RX Strict SFD 10.2.2.3. Check RX FCS 10.2.2.4. Handle RX Malformed Packet 10.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames 10.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 10.2.2.7. Inter-Packet Gap
10.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
10.2.3.1. Conditions Triggering XOFF Frame Transmission 10.2.3.2. Conditions Triggering XON Frame Transmission 10.2.3.3. Pause Control and Generation Interface 10.2.3.4. Pause Control Frame Filtering
10.3. PCS, OTN, and FlexE Modes x
10.3.1. PCS Mode 10.3.2. OTN Mode 10.3.3. FlexE Mode
10.4. Precision Time Protocol Interface x
10.4.1. Features 10.4.2. PTP User Flow 10.4.3. Make PTP UI Adjustments 10.4.4. Reference Time Interval
10.4.2. PTP User Flow x
10.4.2.1. PTP TX User Flow 10.4.2.2. PTP RX User Flow
10.4.3. Make PTP UI Adjustments x
10.4.3.1. Adjust TX UI 10.4.3.2. Adjust RX UI
11. Appendix B: Configuration Registers x
11.1. Ethernet Avalon® Memory-Mapped Interface Address Space 11.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Troubleshoot and Diagnose Issues
10. Appendix A: Functional Description
11. Appendix B: Configuration Registers
12. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex 3 FPGAs and SoCs

4.2. Implement Required Resets

The GTS Ethernet Intel® FPGA Hard IP consists of four main reset ports, five soft datapath, and statistics register resets for Ethernet reset ports.
Figure 21. Conceptual View of General IP Core Reset Logic
Note: When RX MAC is in reset, TX MAC can only transmit idles and remote fault indications if link fault signaling is enabled. The o_tx_ready signals remains low.

The following table lists which blocks are reset by different reset signals:

Table 22.  Reset Signal Functions
Reset Signal PHY Datapath Stats Soft CSRs
  TX RX MAC TX MAC RX PCS TX PCS RX MAC TX MAC RX  
Port Reset
i_rst_n Y Y Y Y Y Y Y Y -
i_tx_rst_n Y - Y - Y - Y - -
i_rx_rst_n - Y - Y - Y - Y -
i_reconfig_reset - - - - - - - - Y
Register Resets
eio_sys_rst Y Y Y Y Y Y Y Y -
soft_tx_rst Y - Y - Y - Y - -
soft_rx_rst - Y - Y - Y - Y -
rst_tx_stats - - - - - - Y - -
rst_rx_stats - - - - - - - Y -

The IP core has four asynchronous reset inputs, which are internally synchronized to their respective clock domains.

Table 23.  Reset Signals
Signal Description
Input signals
i_rst_n

Active-low reset asynchronous signal. Do not deassert until the o_rst_ack_n asserts. Refer to Reset Signal Functions for a list of blocks reset by this signal.

This reset leads to assertion of the o_rst_ack_n output signal.

i_tx_rst_n Active-low reset asynchronous signal. Do not deassert until the o_tx_rst_ack_n asserts.
i_rx_rst_n

Active-low reset asynchronous signal. Do not deassert until the o_rx_rst_ack_n asserts.

i_reconfig_reset

Active-high reconfiguration reset signal. Resets the entire reconfiguration clock domain, including the soft registers (CSRs).

You must assert this reset after power-on or during the IP configuration. The i_reconfig_clk must be stable before de-asserting this reset.

Output signals
o_rst_ack_n

Active-low asynchronous acknowledgement signal for the i_rst_n reset. Do not deassert i_rst_n reset until the o_rst_ack_n asserts.

o_tx_rst_ack_n

Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset. Do not deassert i_tx_rst_n reset until the o_tx_rst_ack_n asserts.

o_rx_rst_ack_n Active-low asynchronous acknowledgement signal for the i_rx_rst_n reset. Do not deassert i_rx_rst_n reset until the o_rx_rst_ack_n asserts.
Status signals
o_tx_lanes_stable

Active-high asynchronous status signal for the TX datapath.

  • Asserts when the TX datapath is ready to send data.
  • Deasserts when i_tx_rst_n/i_rst_n signal is asserted or during the auto-negotiation and link training operation.
o_rx_pcs_ready

Active-high asynchronous status signal for the RX datapath.

  • Asserts when the RX datapath is ready to receive data.
  • Deasserts when i_rx_rst_n/i_rst_n signal is asserted or during the auto-negotiation and link training operation.

Section Content
Reset Sequence
Connect the GTS Reset Sequencer Intel FPGA IP

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