LVDS Tunneling Protocol and Interface IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 844310
Date 2/24/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Configuring and Generating the IP 3. Simulating the IP 4. Validating the IP 5. Troubleshooting and Debugging Issues 6. Appendix A: Functional Description 7. Appendix B: Registers 8. Document Revision History for the LVDS Tunneling Protocol and Interface IP User Guide
1. Overview x
1.1. About the LVDS Tunneling Protocol and Interface IP 1.2. About the Document 1.3. Applicable Applications 1.4. Key Concepts 1.5. IP Design Flow 1.6. Design Considerations/Guidelines
1.1. About the LVDS Tunneling Protocol and Interface IP x
1.1.1. IP Release Information 1.1.2. IP Features 1.1.3. IP High-level Block Diagram 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Acronyms 1.2.4. Reference Documents and Training
1.4. Key Concepts x
1.4.1. Interface Tunneling Principle 1.4.2. LTPI Tunneling Methodology 1.4.3. Clock Topology 1.4.4. LTPI Frame 1.4.5. System-level Block Diagram 1.4.6. Link Management 1.4.7. Signal Description
1.4.4. LTPI Frame x
1.4.4.1. Link Detect and Link Speed Selection Frames 1.4.4.2. Link Detect Frame 1.4.4.3. Link Speed Frame 1.4.4.4. Advertise, Configure, and Accept Frames 1.4.4.5. Advertise Frames 1.4.4.6. Configure Frame 1.4.4.7. Accept Frame 1.4.4.8. LTPI Operational Frames 1.4.4.9. Default I/O Frame 1.4.4.10. Default Data Frame
1.4.6. Link Management x
1.4.6.1. Link Training 1.4.6.2. Link Configuration 1.4.6.3. Operational Mode
1.4.7. Signal Description x
1.4.7.1. Clock and Power Signals 1.4.7.2. Channel Signals 1.4.7.3. Avalon® Memory-Mapped Primary Interface Signals 1.4.7.4. Avalon® Memory-Mapped Secondary Interface Signals 1.4.7.5. Avalon® Memory-Mapped CSR Interface Signals 1.4.7.6. Miscellaneous Interface Signals
2. Configuring and Generating the IP x
2.1. Configuring the Quartus® Prime Pro Edition Project 2.2. Configuring the LVDS Tunneling Protocol and Interface IP 2.3. Generating HDL for Synthesis and Simulation 2.4. Generating the Simulation Design Example 2.5. Compiling the Design Example in Hardware
2.2. Configuring the LVDS Tunneling Protocol and Interface IP x
2.2.1. Configuring the LVDS Tunneling Protocol and Interface IP Parameters
2.3. Generating HDL for Synthesis and Simulation x
2.3.1. Generated File Structure
2.4. Generating the Simulation Design Example x
2.4.1. Generated Directory Structure and Files
3. Simulating the IP x
3.1. Design Example Features 3.2. Design Example Components 3.3. Configuring the Design Example Parameters 3.4. Simulating the Design Example
3.4. Simulating the Design Example x
3.4.1. Simulation Testbench Flow 3.4.2. Simulation Output
6. Appendix A: Functional Description x
6.1. GPIO Channel 6.2. I2C Channel 6.3. UART Channel 6.4. Data Channel 6.5. OEM Channel
1. Overview
2. Configuring and Generating the IP
3. Simulating the IP
4. Validating the IP
5. Troubleshooting and Debugging Issues
6. Appendix A: Functional Description
7. Appendix B: Registers
8. Document Revision History for the LVDS Tunneling Protocol and Interface IP User Guide

1.4.5. System-level Block Diagram

Figure 6. LTPI System-level Block Diagram
The TX (steps 1–4) and RX (steps 5–8) paths in both SCM and HPM work as follows:
  1. The signal on the physical interfaces is captured by the respective LTPI channel in the controller or target.
  2. The LTPI channel controller generates the LTPI frame and CRC checksum.
    1. Each LTPI channels is encoded on dedicated bit fields inside the LTPI Frame. Refer the LTPI Frame section for more details.
  3. The frame is then encoded using 8b/10b encoding.
    1. The frame is extended with frame comma symbol.
  4. The 10b-encoded frame is transmits on the LVDS TX link.
  5. The LVDS traffic is received and downstream into 10b-encoded FIFO buffer.
  6. Frame comma symbol is captured as the beginning of the LTPI frame in the 10b data stream.
    1. The frame is decoded to 8b encoding.
  7. The frame is checked again CRC checksum and decomposed into LTPI channel.
  8. Channel states are being reconstructed on respective channels with channel controllers or target.
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