LVDS Tunneling Protocol and Interface IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 844310
Date 2/24/2025
Public

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Document Table of Contents

1.6. Design Considerations/Guidelines

  1. The IP design supports data rate up to 500 Mbps (x10 250 MHz, DDR mode).
  2. The simulation design example supports fixed data rate configuration at 200 Mbps (x4 100 MHz, DDR mode).
  3. Dynamic reconfiguration PLL is not supported. Selected link configuration (from the LVDS Tunneling Protocol and Interface IP parameter editor) using the clock multiplexer is supported but not dynamically through CSR.
  4. The IP design supports 9600 and 115200 UART baud rates.
  5. The UART flow control is not supported.
  6. The Avalon® memory-mapped CSR interface is utilized exclusively for reading status and error signals, as well as for configuring advertisement capabilities.
  7. Number of normal latency (NL) GPIO Interface must be a value that can be multiplied by factor of 16.
  8. Number of low latency (LL) GPIO Interface is fixed at 16.
  9. You must constraint all the input clocks or signals to the IP.
  10. Hardware design example is not available in the current release of this IP.