LVDS Tunneling Protocol and Interface IP User Guide: Agilex™ 5 FPGAs and SoCs
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1.4.6.1. Link Training
- Achieve DC balance on the link
- Exchange link speed capabilities
- Link detect
- Link speed
Link Detect
In the link detect state, both the SCM FPGA and the HPM FPGA send the link detect frame in both directions, frame as defined in the Link Detect Frame table. The main goals are to establish DC balance on the link and indicate the supported operational frequency. The transmitter (TX) continuously sends the link detect frame, while the receiver (RX) uses these frames for word alignment and start-of-frame detection.
Link Speed
In the link speed state, both SCM FPGA and HPM FPGA start sending the link speed frame in both directions to achieve a target operating speed defined in the Link Speed Frame table. During this state, the link speed frame is continuously transmitted across SCM and HPM.