LVDS Tunneling Protocol and Interface IP User Guide: Agilex™ 5 FPGAs and SoCs
ID
844310
Date
2/24/2025
Public
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1.4.4.1. Link Detect and Link Speed Selection Frames
1.4.4.2. Link Detect Frame
1.4.4.3. Link Speed Frame
1.4.4.4. Advertise, Configure, and Accept Frames
1.4.4.5. Advertise Frames
1.4.4.6. Configure Frame
1.4.4.7. Accept Frame
1.4.4.8. LTPI Operational Frames
1.4.4.9. Default I/O Frame
1.4.4.10. Default Data Frame
2.4. Generating the Simulation Design Example
The LVDS Tunneling Protocol and Interface IP can generate simulation design examples with a fixed IP configuration (refer to the Simulating the Design Example section). You can use these design examples as references for instantiating the IP and reviewing the expected behavior in simulations.
Procedure
- On the Example_design tab, select the Acknowledgement checkbox.
- Select the Example Design HDL Format as follows:
Figure 21. LVDS Tunneling Protocol and Interface IP Parameters—Example_design Tab
Table 42. Design Example Parameters Parameters Value Default Description Example Design HDL Format - Verilog
- VHDL
Verilog Selects the design example in Verilog or VHDL format. - Click the Generate Example Design button.
- Specify the directory for the design example to be generated.
- Once the design example is generated, click the Launch Example Design in Quartus.
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