LVDS Tunneling Protocol and Interface IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 844310
Date 2/24/2025
Public

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3.3. Configuring the Design Example Parameters

You can generate the simulation design example based on a fixed parameter configuration, as listed in the table below.
Table 44.  Parameter Configuration
Parameter Name Value
SYSTEM_CLOCK 100 MHz
LINK_MODE DDR
CAPABILITY X4 (100 MHz)
NL_GPIO 16
LL_GPIO 16
I2C 6
I2C_MODE STANDARD (100 KHz)
UART 2
UART_BAUD 9600
DATA_CHANNEL_MAILBOX_EN 0
OEM_DATA_WIDTH 32
You can find the Verilog design file containing the fixed parameter configuration in the following locations:
  • <design_example_dir>/ltpi_controller/synth/ltpi_controller.v
  • <design_example_dir> /ltpi_target/synth/ltpi_target.v