AN 1000: Drive-on-Chip Design Example: Agilex™ 5 Devices

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ID 826207
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Agilex™ 5 Devices 2. Features of the Drive-on-Chip Design Example for Agilex Devices 3. Getting Started with the Drive-on-Chip Design Example 4. Rebuilding the Drive-on-Chip Design Example 5. Modifying the Design Example for a Different Board 6. About the Scaling of Feedback Signals 7. Motor Control Software 8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices 9. Signals 10. Registers 11. Design Security Recommendations 12. Document Revision History for AN 1000: Drive-on-Chip Design Example for Agilex™ 5 Devices
3. Getting Started with the Drive-on-Chip Design Example x
3.1. Software Requirements for the Drive-on-Chip Design Example for Agilex 5 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Agilex 5 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Agilex 5 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Agilex 5 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Agilex Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Agilex 5 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Agilex 5 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Agilex Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Agilex Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the NiosV/g BSP for the Drive-On-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
6. About the Scaling of Feedback Signals x
6.1. Signal Sensing in Sigma-Delta 6.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 6.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices x
8.1. NiosV/g Processor Subsystem 8.2. Control Subsystem 8.3. Drive Subsystem 8.4. Motor and Power Board Model
8.3. Drive Subsystem x
8.3.1. Six-channel PWM Interface 8.3.2. Drive System Monitor 8.3.3. Quadrature Encoder Interface 8.3.4. Sigma-Delta ADC Interface for Drive Axes 8.3.5. Motor Control Modes 8.3.6. FOC Subsystem
8.3.2. Drive System Monitor x
8.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
8.3.4. Sigma-Delta ADC Interface for Drive Axes x
8.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
8.3.6. FOC Subsystem x
8.3.6.1. DSP Builder Model for the Drive-on-Chip Designs 8.3.6.2. Avalon Memory-Mapped Interface 8.3.6.3. About DSP Builder for Intel FPGAs 8.3.6.4. DSP Builder for Intel FPGAs Folding 8.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 8.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Agilex™ 5 Devices
2. Features of the Drive-on-Chip Design Example for Agilex Devices
3. Getting Started with the Drive-on-Chip Design Example
4. Rebuilding the Drive-on-Chip Design Example
5. Modifying the Design Example for a Different Board
6. About the Scaling of Feedback Signals
7. Motor Control Software
8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices
9. Signals
10. Registers
11. Design Security Recommendations
12. Document Revision History for AN 1000: Drive-on-Chip Design Example for Agilex™ 5 Devices

9. Signals

The signals connect various blocks in the Drive-on-Chip Design Example.
Table 12.  Six-Channel PWM Interface Signals
Signal Name Direction Description
Avalon memory-mapped Interface Signals
sys_clk Input PWM and system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[3:0] Input Avalon memory-mapped address bus
avs_writedata[31:0] Input Avalon memory-mapped write data bus
avs_readdata[31:0] Output Avalon memory-mapped read data bus
Conduit Signals
pwm_clk Input PWM carrier clock.
pwm_reset_n Input Reset signal, active low.
pwm_control[2:0] Input

en_upper: upper switch enable from drive system monitor.

en_lower: lower switch enable from drive system monitor.

pwm_enable: PWM enable from drive system monitor

vu_pwm Input PWM value for phase U voltage
vv_pwm Input PWM value for hase V voltage
vw_pwm Input PWM value for hase W voltage
u_h Output Motor phase phase U upper gate drive
u_l Output Motor phase phase U lower gate drive
v_h Output Motor phase phase V upper gate drive
v_l Output Motor phase phase V lower gate drive
w_h Output Motor phase phase W upper gate drive
w_l Output Motor phase phase W lower gate drive
sync_in Input Synchronization signal for multiple PWM modules
sync_out Output Synchronization signal for multiple PWM modules
encoder_strobe_n Output Strobe signal for encoder.
start_adc Output ADC start conversion signal
Table 13.  Drive System Monitor Interface Signals
Signal Name Direction Description
Avalon memory-mapped Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[0:0] Input Avalon memory-mapped address bus
avs_writedata[31:0] Input Avalon memory-mapped write data bus
avs_readdata[31:0] Output Avalon memory-mapped read data bus
Conduit Signals
overcurrent Input Overcurrent status
overvoltage Input Overvoltage status
undervoltage Input Undervoltage status
chopper Input Chopper status
dc_link_clk_err Input Clock monitor status
mosfet_err Input MOSFET transistor error status
error_out Output Error output
overcurrent_latch Output Latched overcurrent status
overvoltage_latch Output Latched overvoltage status
undervoltage_latch Output Latched undervoltage status
dc_link_clk_err_latch Output Latched clock monitor status
mosfet_err_latch Output Latched MOSFET error status
chopper_latch Output Latched chopper status
pwm_control[2:0] Output PWM control
Table 14.  Quadrature Encoder Interface Signals
Signal Name Direction Description
Avalon memory-mapped Interface Signals
clk Input FPGA system clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[3:0] Input Avalon memory-mapped address bus
avs_writedata[31:0] Input Avalon memory-mapped write data bus
avs_readdata[31:0] Output Avalon memory-mapped read data bus
Conduit Signals
strobe Input Capture strobe
QEP_A Input Quadrature phase A
QEP_B Input Quadrature phase B
QEP_I Input Quadrature index
Table 15.  Sigma-Delta ADC Interface Signals
Signal Name Direction Description
Avalon memory-mapped Interface Signals
clk Input FPGA system clock input
clk_adc Input ADC clock input
reset_n Input System reset signal, active low
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[3:0] Input Avalon memory-mapped address bus
avs_writedata[31:0] Input Avalon memory-mapped write data bus
avs_readdata[31:0] Output Avalon memory-mapped read data bus
avs_irq Output Interrupt request
Conduit Signals
start Input Start conversion signal
sync_dat_u Input Phase U sigma-delta bitstream
sync_dat_v Input Phase V sigma-delta bitstream
sync_dat_w Input Phase W sigma-delta bitstream
Iu_reg[15:0] Output Registers to hold synchronized phase U current
Iw_reg[15:0] Output Registers to hold synchronized phase W current
Iu_reg_156[15:0] Output Registers to hold free running phase U current, not in use.
Iw_reg_156[15:0] Output Registers to hold free running phase W current, not in use.
overcurrent Output Overcurrent status
Table 16.  FOC Subsystem Interface Signals
Signal Name Direction Description
Avalon memory-mapped Interface Signals
clk Input FPGA system clock input
areset Input System reset signal, asynchronous active low
h_areset Input System reset signal, asynchronous active high
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[5:0] Input Avalon memory-mapped address bus
avs_writedata[31:0] Input Avalon memory-mapped write data bus
avs_readdata[31:0] Output Avalon memory-mapped read data bus
readdatavalid Output Avalon memory-mapped read valid signal
waitrequest Output Avalon memory-mapped wait request signal
Conduit Signals
Iu[15:0] Input Phase U current phase U current
Iw[15:0] Input Phase W current phase W current
vu_pwm Output PWM value for phase U voltage
vv_pwm Output PWM value for phase V voltage
vw_pwm Output PWM value for phase W voltage
Table 17.   Motor and Power Board Model Interface Signals
Signal Name Direction Description
Avalon memory-mapped Interface Signals
clk Input PWM and system clock input
areset Input System reset signal, active high
h_areset Input DSP delay reset signal, active high
avs_read_n Input Avalon memory-mapped read strobe, active low
avs_write_n Input Avalon memory-mapped write strobe, active low
avs_address[5:0] Input Avalon memory-mapped address bus
avs_writedata[31:0] Input Avalon memory-mapped write data bus
avs_readdata[31:0] Output Avalon memory-mapped read data bus
readdatavalid Output Avalon memory-mapped read valid signal
waitrequest Output Avalon memory-mapped wait request signal
Conduit Signals
u_h Input Motor phase phase U upper gate drive
u_l Input Motor phase phase U lower gate drive
v_h Input Motor phase phase V upper gate drive
v_l Input Motor phase phase V lower gate drive
w_h Input Motor phase phase W upper gate drive
w_l Input Motor phase phase W lower gate drive
ia_sd Output Phase current A for sigma-delta ADC
ib_sd Output Phase current B for sigma-delta ADC
ic_sd Output Phase current C for sigma-delta ADC
Va_sd Output Phase voltage A for sigma-delta ADC
Vb_sd Output Phase voltage B for sigma-delta ADC
Vc_sd Output Phase voltage C for sigma-delta ADC
QEP_A Output Quadrature phase A
QEP_B Output Quadrature phase B
Theta_one_turn_k [15:0] Output Angular displacement per one turn at the k-th step, data type: ufix16_en16
V_DC_link_sd Output Motor input voltage for sigma-delta ADC
Level Two Title