AN 1000: Drive-on-Chip Design Example: Agilex™ 5 Devices
ID
826207
Date
7/08/2024
Public
1. About the Drive-on-Chip Design Example for Agilex™ 5 Devices
2. Features of the Drive-on-Chip Design Example for Agilex Devices
3. Getting Started with the Drive-on-Chip Design Example
4. Rebuilding the Drive-on-Chip Design Example
5. Modifying the Design Example for a Different Board
6. About the Scaling of Feedback Signals
7. Motor Control Software
8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices
9. Signals
10. Registers
11. Design Security Recommendations
12. Document Revision History for AN 1000: Drive-on-Chip Design Example for Agilex™ 5 Devices
3.1. Software Requirements for the Drive-on-Chip Design Example for Agilex 5 Devices
3.2. Hardware Requirements for the Drive-on-Chip Design Example for Agilex 5 Devices
3.3. Downloading and Installing the Design
3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Agilex 5 Devices
3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Agilex 5 Devices
3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Agilex Devices
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Agilex 5 Devices with Python GUI
8.3.6.1. DSP Builder Model for the Drive-on-Chip Designs
8.3.6.2. Avalon Memory-Mapped Interface
8.3.6.3. About DSP Builder for Intel FPGAs
8.3.6.4. DSP Builder for Intel FPGAs Folding
8.3.6.5. DSP Builder for Intel FPGAs Design Guidelines
8.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
2. Features of the Drive-on-Chip Design Example for Agilex Devices
- Multiple field-oriented control (FOC) loop implementations:
- Fixed-point implementation with Nios V/g processors targeting Agilex devices.
- Fixed-point accelerator implementations designed using Simulink model-based design flow with DSP Builder for Intel FPGAs.
- Selectable 16, 32, or 64 kHz control loop update.
- Integration in a single Agilex FPGA of single and multiaxis motor control IP including:
- High performance pulse-width modulation (PWM) IP at 300 MHz for two-level insulated gate bipolar transistor (IGBT) or MOSFET power stages.
- Sigma delta ADC interfaces for motor current feedback and DC link voltage measurement.
- Multiple position feedback interfaces (default quadrature encoder).
- Open loop modes for troubleshooting the adaptability of the Drive-on-Chip design to other motor and power stage setups.
- Open loop mode selectable between 16 and 32 kHz
- Motor model based on the characteristics of the Tandem Motion 48V power board and Tamagawa TS4747N3200E600 motor on FPGA logic.
- Python-based GUI for motor feedback information, debugging and control of motors.