AN 1000: Drive-on-Chip Design Example: Agilex™ 5 Devices

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ID 826207
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-on-Chip Design Example for Agilex™ 5 Devices 2. Features of the Drive-on-Chip Design Example for Agilex Devices 3. Getting Started with the Drive-on-Chip Design Example 4. Rebuilding the Drive-on-Chip Design Example 5. Modifying the Design Example for a Different Board 6. About the Scaling of Feedback Signals 7. Motor Control Software 8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices 9. Signals 10. Registers 11. Design Security Recommendations 12. Document Revision History for AN 1000: Drive-on-Chip Design Example for Agilex™ 5 Devices
3. Getting Started with the Drive-on-Chip Design Example x
3.1. Software Requirements for the Drive-on-Chip Design Example for Agilex 5 Devices 3.2. Hardware Requirements for the Drive-on-Chip Design Example for Agilex 5 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Agilex 5 Devices 3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Agilex 5 Devices 3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Agilex Devices 3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Agilex 5 Devices with Python GUI
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Agilex 5 Devices with Python GUI x
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Agilex Devices 3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Agilex Devices 3.7.3. Tuning the PI Controller Gains 3.7.4. Controlling the Speed and Position Demonstrations 3.7.5. Monitoring Performance
4. Rebuilding the Drive-on-Chip Design Example x
4.1. Generating the Platform Designer System 4.2. Compiling the Hardware in the Intel Quartus Prime Software 4.3. Generating and Building the NiosV/g BSP for the Drive-On-Chip Design Example 4.4. Software Application Configuration Files
4.4. Software Application Configuration Files x
4.4.1. Defining a New Motor or Encoder Type 4.4.2. Real Time Operating System Specific Configuration Files
6. About the Scaling of Feedback Signals x
6.1. Signal Sensing in Sigma-Delta 6.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 6.3. Scale Factors for the Drive-on-Chip Design Example in the GUI
8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices x
8.1. NiosV/g Processor Subsystem 8.2. Control Subsystem 8.3. Drive Subsystem 8.4. Motor and Power Board Model
8.3. Drive Subsystem x
8.3.1. Six-channel PWM Interface 8.3.2. Drive System Monitor 8.3.3. Quadrature Encoder Interface 8.3.4. Sigma-Delta ADC Interface for Drive Axes 8.3.5. Motor Control Modes 8.3.6. FOC Subsystem
8.3.2. Drive System Monitor x
8.3.2.1. Drive System Monitor States for the Drive-on-Chip Design Example
8.3.4. Sigma-Delta ADC Interface for Drive Axes x
8.3.4.1. Offset Adjustment for Sigma-Delta ADC Interface
8.3.6. FOC Subsystem x
8.3.6.1. DSP Builder Model for the Drive-on-Chip Designs 8.3.6.2. Avalon Memory-Mapped Interface 8.3.6.3. About DSP Builder for Intel FPGAs 8.3.6.4. DSP Builder for Intel FPGAs Folding 8.3.6.5. DSP Builder for Intel FPGAs Design Guidelines 8.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
1. About the Drive-on-Chip Design Example for Agilex™ 5 Devices
2. Features of the Drive-on-Chip Design Example for Agilex Devices
3. Getting Started with the Drive-on-Chip Design Example
4. Rebuilding the Drive-on-Chip Design Example
5. Modifying the Design Example for a Different Board
6. About the Scaling of Feedback Signals
7. Motor Control Software
8. Functional Description of the Drive-on-Chip Design Example for Agilex 5 Devices
9. Signals
10. Registers
11. Design Security Recommendations
12. Document Revision History for AN 1000: Drive-on-Chip Design Example for Agilex™ 5 Devices

3.3. Downloading and Installing the Design

The download for the Drive-on-Chip Design Example for Agilex™ 5 Devices is a .par file.
  1. Download the relevant design .par file for your development kit and power board from the Intel FPGA Design Store.
  2. Install the design for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit by clicking. DOC_TANDEM_MOTORSIM_AGILEX5.par
    Alternatively use Quartus Prime command line to open it: >> quartus DOC_TANDEM_MOTORSIM_AGILEX5.par
    The contents of the .par file open into the working directory.
    Figure 3. Directory Structure

    The FPGA programming files are in the <project>/quartus/output_files/top.sof directory

    The Nios V programming files are in the <project>/software/dniosv_subsystem/build/bin/app.elf directory

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