DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
ID
823560
Date
8/15/2025
Public
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode
1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connecter with Bitec Rev 8 Daughter Card
3. DisplayPort SST Parallel Loopback without PCR Design Example
The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source.
Quartus Prime generates either a duplex or dual simplex PHY design example depending on the board type, FMC target, and lane count. Both structures offer identical features and functionality.