DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

ID 823560
Date 8/15/2025
Public
Document Table of Contents

3. DisplayPort SST Parallel Loopback without PCR Design Example

The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source.

Quartus Prime generates either a duplex or dual simplex PHY design example depending on the board type, FMC target, and lane count. Both structures offer identical features and functionality.