DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. DisplayPort SST Parallel Loopback without PCR Design Example 4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example 5. DisplayPort SST TX-Only Design Example 6. DisplayPort SST RX-Only Design Example 7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating the Nios V .elf File 1.7. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort IP Design Examples x
2.1. Design Components 2.2. DisplayPort IP Design Example Clock Domains 2.3. Interface Signals and Parameters 2.4. Simulation Testbench 2.5. DisplayPort Duplex or Dual Simplex Design Examples
2.5. DisplayPort Duplex or Dual Simplex Design Examples x
2.5.1. DisplayPort Duplex Designs 2.5.2. DisplayPort Dual-Simplex Designs
3. DisplayPort SST Parallel Loopback without PCR Design Example x
3.1. Features 3.2. Functional Description
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example x
4.1. Features 4.2. Functional Description
5. DisplayPort SST TX-Only Design Example x
5.1. DisplayPort SST TX-Only Features 5.2. DisplayPort SST TX-Only Functional Description
6. DisplayPort SST RX-Only Design Example x
6.1. DisplayPort SST RX-Only Features 6.2. DisplayPort SST RX-Only Functional Description
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

2.3. Interface Signals and Parameters

The following tables list the signals and parameter for the DisplayPort IP design example.
Table 8.  Top-Level Parameters
Parameter Value Description
RX_MAX_LANE_COUNT 1, 2 or 4 DP RX Maximum Lane Count
TX_MAX_LANE_COUNT 1, 2 or 4 DP TX Maximum Lane Count
RX_MAX_LINK_RATE 1, 4, 6, 10, 20, 30 (decimal)

DP Rx Maximum Data Rate

6: RBR, 10:HBR, 20: HBR2, 30: HBR3, 1: UHBR10, 4: UHBR13.5
TX_MAX_LINK_RATE 1, 4, 6, 10, 20, 30 (decimal)

DP TX Maximum Data Rate

6: RBR, 10: HBR, 20: HBR2, 30: HBR3, 1: UHBR10, 4: UHBR13.5
RX_PMA_WIDTH 40, 64

DP Rx Parallel Data width

RBR-HBR3: 40 bits

UHBR10-UHBR13.5: 64 bits
TX_PMA_WIDTH 40, 64

DP TX Parallel Data width

RBR-HBR3: 40 bits

UHBR10-UHBR13.5: 64 bits
RX_VIDEO_BPC 6, 8, 10, 12, 16 DP RX Video Bit per Component
TX_VIDEO_BPC 6, 8, 10, 12, 16 DP TX Video Bit per Component
Table 9.  Top-Level Signals
Signal Direction Width Description
On-board Oscillator Signal
refclk_150 Input 1 150 MHz clock source used as System PLL reference clock
core_refclk_100 Input 1 100 MHz clock source used as IOPLL reference clock and Avalon® memory-mapped management clock
User Push Buttons and LEDs
user_pb[0] Input 1 Push button to trigger MSA print out during debug
cpu_resetn Input 1 Global reset
DisplayPort FMC Daughter Card Pins
fmc_rx_p/n Input N DisplayPort RX serial data
Note: N = RX maximum lane count
fmc_tx_p/n Output N DisplayPort TX serial data
Note: N = TX maximum lane count
fmc_dp_rx_cable_detect Input 1 DisplayPort RX cable detect
1 = Cable detected
0 = Cable not detected
fmc_dp_rx_pwr_detect Input 1 DisplayPort RX power detect
1 = Power not detected
0 = Power detected
fmc_dp_rx_aux_in Input 1 DisplayPort RX Aux In
fmc_dp_rx_aux_out Output 1 DisplayPort RX Aux Out
fmc_dp_rx_aux_oe Output 1 DisplayPort RX Aux OE
fmc_dp_rx_hpd Output 1 DisplayPort RX HPD
1 = HPD asserted
0 = HPD deasserted
fmc_dp_tx_hpd Input 1 DisplayPort TX HPD
1 = HPD asserted
0 = HPD deasserted
fmc_dp_tx_aux_in Input 1 DisplayPort TX Aux In
fmc_dp_tx_aux_out Output 1 DisplayPort TX Aux Out
fmc_dp_tx_aux_oe Output 1 DisplayPort TX Aux OE
fmc_dp_tx_cad Output 1 TX CAD for Bitec FMC
Table 10.  DisplayPort IP Signals (Platform Designer System)
Signal Direction Width Description
Clock and Reset
mgmt_clk_in_clk Input 1 100 MHz clock to CPU sub-system
cpu_reset_bridge_in_reset_n Input 1 Reset to CPU sub-system (active low)
DisplayPort RX Signals
dp_rx_reset_bridge_in_reset_n Input 1 Reset to RX sub-system (active low)
dp_rx_clk_16_in_clk Input 1 RX Auxiliary clock (16 MHz)
dp_rx_pio_0_in_port Input 1 Push button I/O for debug purpose
dp_rx_dp_sink_rx_audio_valid Output 1 RX Audio Interface
dp_rx_dp_sink_rx_audio_mute Output 1
Note: M = RX audio channel
dp_rx_dp_sink_rx_audio_infoframe Output 40 —
dp_rx_dp_sink_rx_audio_lpcm_data Output M*32 —
dp_rx_dp_sink_rx_aux_in Input 1 RX auxiliary interface
dp_rx_dp_sink_rx_aux_out Output 1
dp_rx_dp_sink_rx_aux_oe Output 1
dp_rx_dp_sink_rx_hpd Output 1 RX HPD
dp_rx_dp_sink_rx_cable_detect Input 1 RX cable detect (active high)
dp_rx_dp_sink_rx_pwr_detect Input 1 RX power detect (active high)
dp_rx_dp_sink_rx_msa Output 217 DisplayPort RX MSA
dp_rx_dp_sink_rx_lane_count Output 5 DisplayPort RX lane count
dp_rx_dp_sink_rx_link_rate_8bits Output 8 RX Link Rate 8-bit indicator, used in transceiver reconfiguration management
RBR: 0x06
HBR: 0x0A
HBR2: 0x14
HBR3: 0x1E
UHBR10: 0x01
UHBR13.5: 0x04
dp_rx_dp_sink_rx_ss_valid Output 1 DisplayPort RX secondary stream interface
dp_rx_dp_sink_rx_ss_data Output 160
dp_rx_dp_sink_rx_ss_sop Output 1
dp_rx_dp_sink_rx_ss_eop Output 1
dp_rx_dp_sink_rx_ss_clk Output 1
dp_rx_dp_sink_rx_vid_clk Input 1 DisplayPort RX video stream interface.
dp_rx_dp_sink_rx_vid_sol Output 1
Note: B = RX bits per color, P = RX pixels per clock
dp_rx_dp_sink_rx_vid_eol Output 1 —
dp_rx_dp_sink_rx_vid_sof Output 1 —
dp_rx_dp_sink_rx_vid_eof Output 1 —
dp_rx_dp_sink_rx_vid_locked Output 1 —
dp_rx_dp_sink_rx_vid_interlace Output 1 —
dp_rx_dp_sink_rx_vid_field Output 1 —
dp_rx_dp_sink_rx_vid_overflow Output 1 —
dp_rx_dp_sink_rx_vid_data Output B*P*3 —
dp_rx_dp_sink_rx_vid_valid Output P —
dp_rx_dp_sink_rx_parallel_data Input N *S*10 DisplayPort parallel data from RX Direct PHY
Note: N = RX maximum lane count, S = RX symbols per clock
dp_rx_dp_sink_rx_std_clkout Input 1 CDR clock out from RX Direct PHY
dp_rx_dp_sink_rx_reconfig_req Output 1 Transceiver reconfiguration interface to the RX reconfiguration management module
dp_rx_dp_sink_rx_reconfig_ack Input 1
Note: N = RX maximum lane count
dp_rx_dp_sink_rx_reconfig_busy Input 1 —
dp_rx_dp_sink_rx_bitslip Output N —
dp_rx_dp_sink_rx_cal_busy input N —
dp_rx_dp_sink_rx_analogreset Output N —
dp_rx_dp_sink_rx_digitalreset Output N —
dp_rx_dp_sink_rx_is_lockedtoref Input N —
dp_rx_dp_sink_rx_is_lockedtodata Input N —
dp_rx_dp_sink_rx_set_locktoref Output N —
dp_rx_dp_sink_rx_set_locktodata Output N —
DisplayPort TX Signals
dp_tx_reset_bridge_in_reset_n Input 1 Reset to TX sub-system
dp_tx_clk_16_in_clk Input 1 TX Auxiliary clock (16 MHz)
dp_tx_dp_source_clk_cal Input 1 TX reconfiguration calibration clock
dp_tx_dp_source_tx_audio_valid Input 1 TX audio channel interface
dp_tx_dp_source_tx_audio_mute Input 1
Note: M = TX audio channel
dp_tx_dp_source_tx_audio_lpcm_data Input M*32 —
dp_tx_dp_source_tx_audio_clk Input 1 —
dp_tx_dp_source_tx_aux_in Input 1 TX auxiliary interface
dp_tx_dp_source_tx_aux_out Output 1
dp_tx_dp_source_tx_aux_oe Output 1
dp_tx_dp_source_tx_hpd Input 1 TX HPD
dp_tx_dp_source_tx_link_rate_8bits Output 8 TX Link Rate 8-bit indicator, used in transceiver reconfiguration management
RBR: 0x06
HBR: 0x0A
HBR2: 0x14
HBR3: 0x1E
UHBR10: 0x01
UHBR13.5: 0x04
dp_tx_dp_source_tx_ss_ready Output 1 DisplayPort TX secondary stream interface
dp_tx_dp_source_tx_ss_valid Input 1
dp_tx_dp_source_tx_ss_data Input 128
dp_tx_dp_source_tx_ss_sop Input 1
dp_tx_dp_source_tx_ss_eop Input 1
dp_tx_dp_source_tx_ss_clk Output 1
dp_tx_dp_source_tx_vid_clk Input 1 DisplayPort TX video stream (VYSNC/HSYNC/DE) interface (only used when TX_SUPPORT_IM_ENABLE = 0)
dp_tx_dp_source_tx_vid_data Input B*P*3
Note: B = TX bits per color, P = TX pixels per clock
dp_tx_dp_source_tx_vid_v_sync Input P —
dp_tx_dp_source_tx_vid_h_sync Input P —
dp_tx_dp_source_tx_vid_de Input P —
dp_tx_dp_source_tx_im_clk Input 1 DisplayPort TX video image interface (only used when TX_SUPPORT_IM_ENABLE = 1)
dp_tx_dp_source_tx_im_sol Input 1
Note: B = TX bits per color, P = TX pixels per clock
dp_tx_dp_source_tx_im_eol Input 1 —
dp_tx_dp_source_tx_im_sof Input 1 —
dp_tx_dp_source_tx_im_eof Input 1 —
dp_tx_dp_source_tx_im_data Input B*P*3 —
dp_tx_dp_source_tx_im_valid Input 1 —
dp_tx_dp_source_tx_im_locked Input 1 —
dp_tx_dp_source_tx_im_interlace Input 1 —
dp_tx_dp_source_tx_im_field Input 1 —
dp_tx_dp_source_tx_parallel_data Output N*S*10 DisplayPort parallel data to TX Direct PHY
Note: N = TX maximum lane count, S = TX symbols per clock
dp_tx_dp_source_tx_std_clkout Input 1 TX Direct PHY clock out
dp_tx_dp_source_tx_pll_locked Input 1 TX PLL locked indicator
dp_tx_dp_source_tx_reconfig_req Output 1 Transceiver Reconfiguration interface to TX reconfiguration management module
dp_tx_dp_source_tx_reconfig_ack Input 1
Note: N = TX maximum lane count
dp_tx_dp_source_tx_reconfig_busy Input 1 —
dp_tx_dp_source_tx_pll_powerdown Output 1 —
dp_tx_dp_source_tx_analog_reconfig_req Output 1 —
dp_tx_dp_source_tx_analog_reconfig_ack Input 1 —
dp_tx_dp_source_tx_analog_reconfig_busy Input 1 —
dp_tx_dp_source_tx_vod Output N*2 —
dp_tx_dp_source_tx_emp Output N*2 —
dp_tx_dp_source_tx_analogreset Output N —
dp_tx_dp_source_tx_digitalreset Output N —
dp_tx_dp_source_tx_cal_busy Input N —
Table 11.  RX PHY Top-Level Signals
Signal Direction Width Description
mgmt_clk Input 1 RX reconfiguration management clock (100 MHz)
mgmt_resetn Input 1 RX reconfiguration system reset (active low)
sysclk_700 Input 1 System PLL reference clock from System PLL IP (700 MHz)
sysclk_700_locked Input 1 System PLL IP Locked Signal
refclk_150 Input 1 RX Direct PHY CDR reference clock (150 MHz)
rss_clk Input 1 Internal Reset Sequencer Clock from Reset-Sequencer IP
rss_req Output N Internal GTS Lane Reset Req
Note: N = RX maximum lane count (1, 2, or 4)
rss_grant Input N Internal GTS Lane Reset Ack
Note: N = RX maximum lane count (1, 2, or 4)
rx_link_rate Input 8 RX link rate indicator used in transceiver reconfiguration management
rx_lane_count Input 5 RX active lanes
rx_reconfig_en Output 1 RX reconfiguration enable signal
rx_rate_rcfg_req Input 1 RX link rate reconfiguration request
rx_rate_rcfg_ack Output 1 RX link rate reconfiguration has started acknowledgement
rx_rate_rcfg_busy Output 1 RX link rate reconfiguration is in process
rx_clk Output 1 RX CDR Recovered Clock
rx_p/rx_n Input N DisplayPort Serial Data to RX Direct PHY
Note: N = RX maximum lane count (1, 2, or 4)
rx_parallel_data Output S DisplayPort parallel data to DisplayPort RX core
Note: S=PMA_WIDTH (40, 64)
rx_is_lockedtoref Output 1 CDR PLL is locked to RefClock signal
rx_is_lockedtodata Output 1 CDR is locked to incoming data
Table 12.  TX PHY Top-Level Signals
Signal Direction Width Description
mgmt_clk Input 1 TX reconfiguration management clock (100 MHz)
mgmt_resetn Input 1 TX reconfiguration system reset (active low)
sysclk_700 Input 1 System PLL reference clock from System PLL IP (700 MHz)
sysclk_700_locked Input 1 System PLL IP locked signal
refclk_150 Input 1 TX Direct PHY PLL reference clock (150 MHz)
rss_clk Input 1 Internal Reset Sequencer Clock from Reset Sequencer IP
rss_req Output N Internal GTS Lane Reset Req
Note: N = TX maximum lane count (1, 2, or 4)
rss_grant Input N Internal GTS Lane Reset Ack

Note: N = TX maximum lane count (1, 2, or 4)
tx_link_rate Input 8 TX Link Rate indicator used in transceiver reconfiguration management
tx_reconfig_en Output 1 TX reconfiguration enable signal
tx_clk Output 1 Transceiver clock out
tx_p/tx_n Output N DisplayPort Serial Data from Transceiver
Note: N = TX maximum lane count
tx_parallel_data Input S DisplayPort Parallel Data from DisplayPort TX Core
Note: S=PMA_WIDTH (40, 64)
tx_analog_rcfg_req Input 1 Analogue Reconfiguration Request
tx_analog_rcfg_ack Output 1 Analogue reconfiguration acknowledgment
tx_analog_rcfg_vod Input 8 Analogue voltage driver level
tx_analog_rcfg_emp Input 8 Analogue Pre-Emphasis driver level
tx_rate_rcfg_req Input 1 TX link rate reconfiguration request
tx_rate_rcfg_ack Output 1 TX link rate reconfiguration has started acknowledgment
tx_rate_rcfg_busy Output 1 TX link rate reconfiguration is in process
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