DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. DisplayPort SST Parallel Loopback without PCR Design Example 4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example 5. DisplayPort SST TX-Only Design Example 6. DisplayPort SST RX-Only Design Example 7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating the Nios V .elf File 1.7. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort IP Design Examples x
2.1. Design Components 2.2. DisplayPort IP Design Example Clock Domains 2.3. Interface Signals and Parameters 2.4. Simulation Testbench 2.5. DisplayPort Duplex or Dual Simplex Design Examples
2.5. DisplayPort Duplex or Dual Simplex Design Examples x
2.5.1. DisplayPort Duplex Designs DisplayPort PHY IP Duplex Generation Flow 2.5.2. DisplayPort Dual-Simplex Designs
3. DisplayPort SST Parallel Loopback without PCR Design Example x
3.1. Features 3.2. Functional Description
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example x
4.1. Features 4.2. Functional Description
5. DisplayPort SST TX-Only Design Example x
5.1. DisplayPort SST TX-Only Features 5.2. DisplayPort SST TX-Only Functional Description
6. DisplayPort SST RX-Only Design Example x
6.1. DisplayPort SST RX-Only Features 6.2. DisplayPort SST RX-Only Functional Description
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

2.5.1. DisplayPort Duplex Designs

Quartus Prime generates SST Parallel Loopback without PCR and SST Parallel Loopback with AXI4-S Video Interface duplex designs when both the Rx and Tx instances have symmetric lane count and physical channel locations
Figure 9. Duplex PHYThe following figure shows a Duplex PHY with one instance of GTS Direct PHY IP embedded within the DisplayPort PHY IP

DisplayPort PHY IP Duplex Generation Flow

When Quartus Prime generates a duplex design example, a single transceiver IP appears in the top-level Verilog HDL of the design example.
Figure 10. Duplex PHY IP Top-Level Module
The DS tool is grayed out because the design does not include any simplex IPs.
Figure 11. Dual Simplex (DS) Assignment Editor
Level Two Title