DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

ID 823560
Date 8/15/2025
Public
Document Table of Contents

3.2. Functional Description

For the DisplayPort SST parallel loopback without PCR design example.
Figure 13.  Agilex™ 5 DisplayPort SST Parallel Loopback Without Pixel Clock RecoveryThe figure shows the design example with a duplex PHY. Alternatively, Quartus Prime may generate a dual simplex version..
  • For either duplex or dual simplex designs, only the PHY instance alters its structure. The features and functionality of the designs remain unchanged.
  • This design requires the video interface, so you must turn on DisplayPort source’s parameter, Enable Video input image port (TX_VIDEO_IM_ENABLE) before generation as the video image interface is required.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor.