DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
ID
823560
Date
8/15/2025
Public
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode
1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connecter with Bitec Rev 8 Daughter Card
3.2. Functional Description
For the DisplayPort SST parallel loopback without PCR design example.
Figure 13. Agilex™ 5 DisplayPort SST Parallel Loopback Without Pixel Clock RecoveryThe figure shows the design example with a duplex PHY. Alternatively, Quartus Prime may generate a dual simplex version..
- For either duplex or dual simplex designs, only the PHY instance alters its structure. The features and functionality of the designs remain unchanged.
- This design requires the video interface, so you must turn on DisplayPort source’s parameter, Enable Video input image port (TX_VIDEO_IM_ENABLE) before generation as the video image interface is required.
- The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
- The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor.