GTS DisplayPort FPGA IP Design Example User Guide

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ID 823560
Date 12/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. DisplayPort SST Parallel Loopback without PCR Design Example 4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example 5. DisplayPort SST TX-Only Design Example 6. DisplayPort SST RX-Only Design Example 7. Document Revision History for the GTS DisplayPort FPGA IP Design Example User Guide
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating the Nios V .elf File 1.7. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 3 FPGA and SoC C-Series Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode 1.5.4. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with Bitec Rev 8 Daughter Card
2. DisplayPort IP Design Examples x
2.1. Design Components 2.2. DisplayPort IP Design Example Clock Domains 2.3. Interface Signals and Parameters 2.4. Simulation Testbench
3. DisplayPort SST Parallel Loopback without PCR Design Example x
3.1. Features 3.2. Functional Description
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example x
4.1. Features 4.2. Functional Description
5. DisplayPort SST TX-Only Design Example x
5.1. DisplayPort SST TX-Only Features 5.2. DisplayPort SST TX-Only Functional Description
6. DisplayPort SST RX-Only Design Example x
6.1. DisplayPort SST RX-Only Features 6.2. DisplayPort SST RX-Only Functional Description
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the GTS DisplayPort FPGA IP Design Example User Guide

6.1. DisplayPort SST RX-Only Features

The design example includes the following features:
  • Supports RBR, HBR, HBR2, HBR3, UHBR10, and UHBR13.5 Link Rates
  • Supports DisplayPort version 1.4 and 2.1
  • Supports 1,2 and 4 lanes ( Agilex™ 3 devices are only able to generate design example with the maximum of 2 lanes)
  • Supports System PLL or PMA Transceiver modes
  • Provides a sink only demonstration
  • Instantiates a Nios V processor for link management
Level Two Title