Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Quick Start Guide
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Set Up BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. The Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. The Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab 4.3.4.5. The GPIO Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab 4.3.4.3.3. The DP Tab 4.3.4.3.4. The HDMI Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP-2B Tab 4.3.4.4.2. The COMP-3B Tab 4.3.4.4.3. The COMP-3A Tab
4.3.4.5. The GPIO Tab x
4.3.4.5.1. The Push Button Tab 4.3.4.5.2. The Dip Switch Tab 4.3.4.5.3. The I2C Bus Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The System Information 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7.1. Modular Board Primary Connector

Table 16.  Modular Board Primary Connector (J14)
  A B C D
1 +V_HVIO_5A_C2M GND +V_HVIO_5B_C2M SOM_PRSNT_PRI_1
2 GND A5E_JTAG_TDO_M2C_1V8 GND I2C_SCL2_C2M_3V3
3 A5E_JTAG_TCK_C2M_1V8 A5E_JTAG_TDI_C2M_1V8 SOM_RESET_C2M_3V3 I2C_SDA2_C2M_3V3
4 A5E_JTAG_TMS_C2M_1V8 REMOTE_EN_C2M_3V3 A5E_INTN_C2M_1V8 GND
5 SOM_PWR_EN_C2M_3V3 SOM_PWR_OK_M2C_3V3 A5E_NSTATUS_M2C_B2B_1V8 PMBUS_SDA_C2M_3V3
6 PMBUS_SCL_C2M_3V3 A5E_NCONFIG_C2M_B2B_1V8 A5E_INIT_DONE_M2C_B2B_1V8 EN_GROUP2_M2C_3V3
7 GND FAN_PWM_C2M_3V3 A5E_CONF_DONE_M2C_B2B_1V8 PG_GROUP2_C2M_3V3_R
8 I2C_SCL1_C2M_3V3 FAN_TACH_C2M_3V3 A5E_AS_NCSO_MSEL0_C2M_1V8 AG5E_MSEL1_C2M_1V8
9 I2C_SDA1_C2M_3V3 GND AG5E_MSEL2_C2M_1V8 GND
10 GND A5E_UX_1C_TX3_DN GND A5E_UX_1C_RX3_DN
11 GND A5E_UX_1C_TX3_DP GND A5E_UX_1C_RX3_DP
12 A5E_UX_1C_TX0_DN GND A5E_UX_1C_RX0_DN GND
13 A5E_UX_1C_TX0_DP GND A5E_UX_1C_RX0_DP GND
14 GND A5E_UX_1C_RX1_DN GND SEU_ERROR_M2C_1V8
15 GND A5E_UX_1C_RX1_DP GND NC
16 A5E_UX_1C_TX1_DN GND ADDR0_M2C_3V3 GND
17 A5E_UX_1C_TX1_DP GND ADDR1_M2C_3V3 GND
18 GND A5E_UX_1C_REC_CLK_DN GND CLK_A5E_UX_1C_R_C_DN
19 GND A5E_UX_1C_REC_CLK_DP GND CLK_A5E_UX_1C_R_C_DP
20 NC GND NC GND
21 NC GND NC GND
22 GND NC GND NC
23 GND NC GND NC
24 NC GND NC GND
25 NC GND NC GND
26 GND NC GND NC
27 GND NC GND NC
28 NC GND NC GND
29 NC GND NC GND
30 GND A5E_UX_1B_TX2_DN GND A5E_UX_1B_TX3_DN
31 GND A5E_UX_1B_TX2_DP GND A5E_UX_1B_TX3_DP
32 A5E_UX_1B_RX2_DN GND A5E_UX_1B_RX3_DN GND
33 A5E_UX_1B_RX2_DP GND A5E_UX_1B_RX3_DP GND
34 GND A5E_UX_1B_TX0_DN GND A5E_UX_1B_TX1_DN
35 GND A5E_UX_1B_TX0_DP GND A5E_UX_1B_TX1_DP
36 A5E_UX_1B_RX0_DN GND A5E_UX_1B_RX1_DN GND
37 A5E_UX_1B_RX0_DP GND A5E_UX_1B_RX1_DP GND
38 GND CLK_A5E_UX_1B_R_DN GND CLK_A5E_UX_1B_G_DN
39 GND CLK_A5E_UX_1B_R_DP GND CLK_A5E_UX_1B_G_DP
40 A5E_UX_1A_RX2_DN GND A5E_UX_1A_RX3_DN GND
41 A5E_UX_1A_RX2_DP GND A5E_UX_1A_RX3_DP GND
42 GND A5E_UX_1A_TX0_DN GND A5E_UX_1A_TX3_DN
43 GND A5E_UX_1A_TX0_DP GND A5E_UX_1A_TX3_DP
44 A5E_UX_1A_RX0_DN GND A5E_UX_1A_RX1_DN GND
45 A5E_UX_1A_RX0_DP GND A5E_UX_1A_RX1_DP GND
46 GND A5E_UX_1A_TX1_DN GND A5E_UX_1A_TX2_DN
47 GND A5E_UX_1A_TX1_DP GND A5E_UX_1A_TX2_DP
48 CLK_A5E_UX_1A_R_DN GND CLK_A5E_UX_1A_G_DN GND
49 CLK_A5E_UX_1A_R_DP GND CLK_A5E_UX_1A_G_DP GND
50 GND A5E_HVIO_5B_2 GND A5E_HVIO_5B_18
51 A5E_HVIO_5B_1 GND A5E_HVIO_5B_7 GND
52 A5E_HVIO_5B_9 A5E_HVIO_5B_20 A5E_HVIO_5B_3 A5E_HVIO_5B_13
53 GND A5E_HVIO_5B_19 GND A5E_HVIO_5B_11
54 A5E_HVIO_5B_4 A5E_HVIO_5B_5 A5E_HVIO_5B_15 A5E_HVIO_5B_14
55 A5E_HVIO_5B_10 GND A5E_HVIO_5B_17 GND
56 A5E_HVIO_5B_6 A5E_HVIO_5B_8 A5E_HVIO_5B_12 A5E_HVIO_5B_16
57 GND A5E_HVIO_5A_1 GND A5E_HVIO_5A_7
58 A5E_HVIO_5A_3 A5E_HVIO_5A_2 A5E_HVIO_5A_14 A5E_HVIO_5A_12
59 A5E_HVIO_5A_4 GND A5E_HVIO_5A_13 GND
60 A5E_HVIO_5A_15 A5E_HVIO_5A_16 A5E_HVIO_5A_8 A5E_HVIO_5A_11
61 GND A5E_HVIO_5A_10 GND A5E_HVIO_5A_6
62 A5E_HVIO_5A_19 A5E_HVIO_5A_5 A5E_HVIO_5A_17 A5E_HVIO_5A_9
63 A5E_HVIO_5A_20 GND A5E_HVIO_5A_18 GND
64 A5E_HSIO_2A_T23_DN A5E_HSIO_2A_T23_DP A5E_HSIO_2A_T24_DP A5E_HSIO_2A_T24_DN
65 GND A5E_HSIO_2A_B5_DP GND A5E_HSIO_2A_B23_DP
66 A5E_HSIO_2A_B6_DP A5E_HSIO_2A_B5_DN A5E_HSIO_2A_B24_DP A5E_HSIO_2A_B23_DN
67 A5E_HSIO_2A_B6_DN GND A5E_HSIO_2A_B24_DN GND
68 A5E_HSIO_2A_B17_DP A5E_HSIO_2A_B17_DN A5E_HSIO_2A_B4_DP A5E_HSIO_2A_B4_DN
69 GND A5E_HSIO_2A_B3_DP GND A5E_HSIO_2A_B22_DP
70 A5E_HSIO_2A_B18_DP A5E_HSIO_2A_B3_DN A5E_HSIO_2A_T22_DP A5E_HSIO_2A_B22_DN
71 A5E_HSIO_2A_B18_DN GND A5E_HSIO_2A_T22_DN GND
72 A5E_HSIO_2A_T21_DP A5E_HSIO_2A_T21_DN A5E_HSIO_2A_B2_DP A5E_HSIO_2A_B2_DN
73 GND A5E_HSIO_2A_T5_DP GND A5E_HSIO_2A_B21_DP
74 A5E_HSIO_2A_B1_DP A5E_HSIO_2A_T5_DN A5E_HSIO_2A_T20_DP A5E_HSIO_2A_B21_DN
75 A5E_HSIO_2A_B1_DN GND A5E_HSIO_2A_T20_DN GND
76 A5E_HSIO_2A_B16_DP A5E_HSIO_2A_B16_DN A5E_HSIO_2A_T6_DP A5E_HSIO_2A_T6_DN
77 GND A5E_HSIO_2A_T19_DP GND A5E_HSIO_2A_B20_DP
78 A5E_HSIO_2A_B15_DP A5E_HSIO_2A_T19_DN A5E_HSIO_2A_T4_DP A5E_HSIO_2A_B20_DN
79 A5E_HSIO_2A_B15_DN GND A5E_HSIO_2A_T4_DN GND
80 A5E_HSIO_2A_T18_DP A5E_HSIO_2A_T18_DN A5E_HSIO_2A_B14_DP A5E_HSIO_2A_B14_DN
81 GND A5E_HSIO_2A_T2_DP GND A5E_HSIO_2A_B13_DN
82 A5E_HSIO_2A_B11_DP A5E_HSIO_2A_T2_DN NC A5E_HSIO_2A_B13_DP
83 A5E_HSIO_2A_B11_DN GND A5E_HSIO_2A_T17_DN GND
84 A5E_HSIO_2A_T16_DP A5E_HSIO_2A_T16_DN A5E_HSIO_2A_T11_DP A5E_HSIO_2A_T11_DN
85 GND A5E_HSIO_2A_T12_DP GND A5E_HSIO_2A_B19_DP
86 A5E_HSIO_2A_T3_DP A5E_HSIO_2A_T12_DN A5E_HSIO_2A_B12_DP A5E_HSIO_2A_B19_DN
87 A5E_HSIO_2A_T3_DN GND A5E_HSIO_2A_B12_DN GND
88 A5E_HSIO_2A_T15_DP A5E_HSIO_2A_T15_DN A5E_HSIO_2A_T10_DP A5E_HSIO_2A_T10_DN
89 GND A5E_HSIO_2A_B10_DP GND A5E_HSIO_2A_T9_DP
90 A5E_HSIO_2A_T1_DN A5E_HSIO_2A_B10_DN A5E_HSIO_2A_B9_DP A5E_HSIO_2A_T9_DN
91 A5E_HSIO_2A_T1_DP GND A5E_HSIO_2A_B9_DN GND
92 A5E_HSIO_2A_T14_DN A5E_HSIO_2A_T14_DP A5E_HSIO_2A_T8_DP A5E_HSIO_2A_T8_DN
93 GND A5E_HSIO_2A_B8_DP GND A5E_HSIO_2A_B7_DP
94 A5E_HSIO_2A_T13_DN A5E_HSIO_2A_B8_DN A5E_HSIO_2A_T7_DP A5E_HSIO_2A_B7_DN
95 A5E_HSIO_2A_T13_DP GND A5E_HSIO_2A_T7_DN GND
96 SOM_PRSNT_PRI_2 +V1P2 GND +V1P2
97 GND GND GND GND
98 +V12P0 +V12P0 +V12P0 +V12P0
99 GND GND GND GND
100 +V12P0 +V12P0 +V12P0 +V12P0
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