Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Quick Start Guide
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Set Up BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. The Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. The Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab 4.3.4.5. The GPIO Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab 4.3.4.3.3. The DP Tab 4.3.4.3.4. The HDMI Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP-2B Tab 4.3.4.4.2. The COMP-3B Tab 4.3.4.4.3. The COMP-3A Tab
4.3.4.5. The GPIO Tab x
4.3.4.5.1. The Push Button Tab 4.3.4.5.2. The Dip Switch Tab 4.3.4.5.3. The I2C Bus Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The System Information 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

6.2. EMIF Pin Swizzling Setting

DQ pins within a DQS group or/and DQS group are swapped to simplify board design.

To achieve the swizzling, you must enter swizzling setting in the Pin Swizzle Map option in the External Memory Interfaces (EMIF) IP parameter editor.

Figure 49. Entering a PIN_SWIZZLE Specification
  1. For DDR4 Bank 2B, use the following settings: 
    BYTE_SWIZZLE_CH0=1,X,X,X,0,2,3,X;
PIN_SWIZZLE_CH0_DQS0=7,5,1,3,4,2,0,6;
PIN_SWIZZLE_CH0_DQS1=9,15,13,11,14,12,8,10;
PIN_SWIZZLE_CH0_DQS2=19,23,21,17,16,18,20,22;
PIN_SWIZZLE_CH0_DQS3=31,29,27,25,26,30,24,28;
  2. For DDR4 Bank 3A, use the following settings: 
    BYTE_SWIZZLE_CH0=0,X,X,X,1,2,3,ECC;
PIN_SWIZZLE_CH0_DQS0=2,0,6,4,7,5,3,1;
PIN_SWIZZLE_CH0_DQS1=14,11,12,8,10,9,13,15;
PIN_SWIZZLE_CH0_DQS2=16,20,22,18,23,21,19,17;
PIN_SWIZZLE_CH0_DQS3=26,30,28,24,25,27,29,31;
PIN_SWIZZLE_CH0_ECC=4,6,2,0,1,7,5,3;
  3. For DDR4 Bank 3B, use the following settings: 
    BYTE_SWIZZLE_CH0=0,X,X,X,1,2,3,ECC;
PIN_SWIZZLE_CH0_DQS0=2,0,6,4,7,3,5,1;
PIN_SWIZZLE_CH0_DQS1=12,14,13,10,8,11,15,9;
PIN_SWIZZLE_CH0_DQS2=16,17,18,19,20,21,22,23;
PIN_SWIZZLE_CH0_DQS3=24,25,26,27,28,29,30,31;
PIN_SWIZZLE_CH0_ECC=0,2,6,4,1,3,7,5;
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