Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Quick Start Guide
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Set Up BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. The Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. The Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab 4.3.4.5. The GPIO Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab 4.3.4.3.3. The DP Tab 4.3.4.3.4. The HDMI Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP-2B Tab 4.3.4.4.2. The COMP-3B Tab 4.3.4.4.3. The COMP-3A Tab
4.3.4.5. The GPIO Tab x
4.3.4.5.1. The Push Button Tab 4.3.4.5.2. The Dip Switch Tab 4.3.4.5.3. The I2C Bus Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The System Information 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7.4. Carrier Board Secondary Connector

Table 19.  Carrier Board Secondary Connector (J13)
  A B C D
1 SOM_PRSNT_SEC_1 +V1P8_HVIO GND +V1P8_HVIO
2 GND DISP_PORT_RX_AUX_DP_SENSE GND A5E_HVIO_6D_14_1V8
3 DISP_PORT_TX_AUX_DRV_OE_1V8 DISP_PORT_RX_AUX_DN_SENSE DISP_PORT_TX_CON_CONFIG1_N_1V8 A5E_HVIO_6D_19_1V8
4 DISP_PORT_TX_AUX_DRV_OUT_1V8 GND DISP_PORT_TX_CON_HPD_N_1V8 GND
5 DISP_PORT_TX_AUX_DRV_IN_1V8 DISP_PORT_RX_AUX_DRV_OE_1V8 DISP_PORT_RX_CON_HPD_1V8 A5E_HVIO_6D_7_1V8
6 GND DISP_PORT_RX_AUX_DRV_OUT_1V8 GND A5E_HVIO_6D_2_1V8
7 A5E_HVIO_6D_5_1V8 DISP_PORT_RX_AUX_DRV_IN_1V8 A5E_HVIO_6D_6_1V8 A5E_HVIO_6D_4_1V8
8 A5E_HVIO_6D_3_1V8 GND A5E_HVIO_6D_1_1V8 GND
9 A5E_HVIO_6C_6_1V8 A5E_HVIO_6C_5_1V8 A5E_HVIO_6C_13_1V8 A5E_HVIO_6C_17_1V8
10 GND A5E_HVIO_6C_7_1V8 GND A5E_HVIO_6C_1_1V8
11 A5E_HVIO_6C_8_1V8 A5E_HVIO_6C_4_1V8 A5E_HVIO_6C_3_1V8 ETH0_INT_N_1V8
12 A5E_HVIO_6C_11_1V8 GND A5E_HVIO_6C_20_1V8 GND
13 A5E_HVIO_6C_12_1V8 A5E_HVIO_6C_9_1V8 A5E_HVIO_6C_2_1V8 ETH1_INT_N_1V8
14 GND A5E_HVIO_6C_14_1V8 GND A5E_HVIO_6C_10_1V8
15 A5E_HVIO_6C_16_1V8 A5E_HVIO_6C_15_1V8 A5E_HVIO_6E_12_1V8 A5E_HVIO_6E_10_1V8
16 A5E_HVIO_6E_18_1V8 GND A5E_HVIO_6E_1_1V8 GND
17 A5E_HVIO_6E_17_1V8 A5E_HVIO_6E_14_1V8 A5E_HVIO_6E_13_1V8 A5E_HVIO_6E_15_1V8
18 GND A5E_HVIO_6E_19_1V8 GND A5E_HVIO_6E_20_1V8
19 A5E_HVIO_6E_7_1V8 A5E_HVIO_6E_4_1V8 A5E_HVIO_6E_2_1V8 A5E_HVIO_6E_11_1V8
20 A5E_HVIO_6E_5_1V8 GND A5E_HVIO_6E_3_1V8 GND
21 A5E_HVIO_6E_6_1V8 A5E_HVIO_6E_8_1V8 A5E_HVIO_6E_9_1V8 A5E_HVIO_6E_16_1V8
22 GND A5E_HVIO_6F_20_1V8 GND A5E_HVIO_6F_16_1V8
23 A5E_HVIO_6F_18_1V8 A5E_HVIO_6F_19_1V8 A5E_HVIO_6F_15_1V8 A5E_HVIO_6F_17_1V8
24 A5E_HVIO_6F_14_1V8 GND A5E_HVIO_6F_13_1V8 GND
25 A5E_HVIO_6F_12_1V8 A5E_HVIO_6F_11_1V8 A5E_HVIO_6F_10_1V8 A5E_HVIO_6F_9_1V8
26 GND A5E_HVIO_6F_8_1V8 GND A5E_HVIO_6F_4_1V8
27 A5E_HVIO_6F_3_1V8 A5E_HVIO_6F_7_1V8 A5E_HVIO_6F_1_1V8 A5E_HVIO_6F_2_1V8
28 A5E_HVIO_6F_5_1V8 GND A5E_HVIO_6F_6_1V8 GND
29 GND PCIE_RX_0_DN GND PCIE_RX_1_DN
30 GND PCIE_RX_0_DP GND PCIE_RX_1_DP
31 PCIE_TX_0_DN GND PCIE_TX_1_DN GND
32 PCIE_TX_0_DP GND PCIE_TX_1_DP GND
33 GND PCIE_RX_2_DN GND PCIE_RX_3_DN
34 GND PCIE_RX_2_DP GND PCIE_RX_3_DP
35 PCIE_TX_2_DN GND PCIE_TX_3_DN GND
36 PCIE_TX_2_DP GND PCIE_TX_3_DP GND
37 GND CLK_SI5518_OUT15_100M_DN GND CLK_SI53254_OUT0_100M_DN
38 GND CLK_SI5518_OUT15_100M_DP GND CLK_SI53254_OUT0_100M_DP
39 PCIE_RX_4_DN GND PCIE_RX_5_DN GND
40 PCIE_RX_4_DP GND PCIE_RX_5_DP GND
41 GND PCIE_TX_4_DN GND PCIE_TX_5_DN
42 GND PCIE_TX_4_DP GND PCIE_TX_5_DP
43 PCIE_RX_6_DN GND PCIE_RX_7_DN GND
44 PCIE_RX_6_DP GND PCIE_RX_7_DP GND
45 GND PCIE_TX_6_DN GND PCIE_TX_7_DN
46 GND PCIE_TX_6_DP GND PCIE_TX_7_DP
47 CLK_SI5518_OUT14_100M_DN GND CLK_SI53254_OUT1_100M_DN GND
48 CLK_SI5518_OUT14_100M_DP GND CLK_SI53254_OUT1_100M_DP GND
49 GND HDMI_RX_3_DN GND HDMI_RX_2_DN
50 GND HDMI_RX_3_DP GND HDMI_RX_2_DP
51 HDMI_TX_CLK_DN GND HDMI_TX_2_DN GND
52 HDMI_TX_CLK_DP GND HDMI_TX_2_DP GND
53 GND HDMI_RX_1_DN GND HDMI_RX_0_DN
54 GND HDMI_RX_1_DP GND HDMI_RX_0_DP
55 HDMI_TX_1_DN GND HDMI_TX_0_DN GND
56 HDMI_TX_1_DP GND HDMI_TX_0_DP GND
57 GND CLK_HDMI_RX_DN GND CLK_MUX_SI5518_OUT16_SI569_100M_DN
58 GND CLK_HDMI_RX_DP GND CLK_MUX_SI5518_OUT16_SI569_100M_DP
59 DISP_PORT_RX_3_DN GND DISP_PORT_RX_2_DN GND
60 DISP_PORT_RX_3_DP GND DISP_PORT_RX_2_DP GND
61 GND DISP_PORT_TX_3_DN GND DISP_PORT_TX_2_DN
62 GND DISP_PORT_TX_3_DP GND DISP_PORT_TX_2_DP
63 DISP_PORT_RX_1_DN GND DISP_PORT_RX_0_DN GND
64 DISP_PORT_RX_1_DP GND DISP_PORT_RX_0_DP GND
65 GND DISP_PORT_TX_1_DN GND DISP_PORT_TX_0_DN
66 GND DISP_PORT_TX_1_DP GND DISP_PORT_TX_0_DP
67 CLK_SI549_DISP_PORT_100M_DN GND CLK_SI5518_OUT17_100M_DN GND
68 CLK_SI549_DISP_PORT_100M_DP GND CLK_SI5518_OUT17_100M_DP GND
69 GND A5E_HVIO_6G_14_1V8 GND A5E_HVIO_6G_17_1V8
70 A5E_HVIO_6G_13_1V8 A5E_HVIO_6G_10_1V8 A5E_HVIO_6G_16_1V8 A5E_HVIO_6G_11_1V8
71 A5E_HVIO_6G_2_1V8 GND A5E_HVIO_6G_19_1V8 GND
72 A5E_HVIO_6G_5_1V8 A5E_HVIO_6G_1_1V8 A5E_HVIO_6G_8_1V8 A5E_HVIO_6G_15_1V8
73 GND A5E_HVIO_6G_7_1V8 GND A5E_HVIO_6G_20_1V8
74 A5E_HVIO_6G_4_1V8 A5E_HVIO_6G_6_1V8 A5E_HVIO_6G_9_1V8 A5E_HVIO_6G_18_1V8
75 A5E_HVIO_6G_3_1V8 GND A5E_HVIO_6G_12_1V8 GND
76 A5E_HVIO_6H_18_1V8 A5E_HVIO_6H_17_1V8 A5E_HVIO_6H_3_1V8 A5E_HVIO_6H_5_1V8
77 GND A5E_HVIO_6H_2_1V8 GND A5E_HVIO_6H_6_1V8
78 A5E_HVIO_6H_7_1V8 A5E_HVIO_6H_11_1V8 A5E_HVIO_6H_12_1V8 A5E_HVIO_6H_4_1V8
79 A5E_HVIO_6H_20_1V8 GND A5E_HVIO_6H_15_1V8 GND
80 A5E_HVIO_6H_19_1V8 A5E_HVIO_6H_8_1V8 A5E_HVIO_6H_16_1V8 A5E_HVIO_6H_1_1V8
81 GND A5E_HVIO_6H_14_1V8 GND A5E_HVIO_6H_13_1V8
82 A5E_HVIO_6H_10_1V8 A5E_HVIO_6H_9_1V8 NC NC
83 NC GND NC GND
84 NC NC NC PCIE0_EDGE_PERST_R_N_3V3
85 GND NC GND NC
86 NC NC TSN_HPS_1PPS_OUT_1V8 TSN_HVIO_1PPS_IN_3V3
87 NC GND TSN_HPS_1PPS_IN_1V8 GND
88 NC NC NC NC
89 GND A5E_HVIO_6B_17_3V3 GND A5E_HVIO_6B_18_3V3
90 SFP28_MOD_DET_3V3 A5E_HVIO_6B_19_3V3 A5E_HVIO_6B_16_3V3 A5E_HVIO_6B_20_3V3
91 SFP28_LOS_3V3 GND A5E_HVIO_6B_11_3V3 GND
92 SFP28_TX_FAULT_3V3 A5E_HVIO_6B_2_3V3 A5E_HVIO_6B_1_3V3 A5E_HVIO_6B_15_3V3
93 GND A5E_HVIO_6B_8_3V3 GND A5E_HVIO_6B_12_3V3
94 SFP28_TX_DISABLE_3V3 A5E_HVIO_6B_7_3V3 A5E_HVIO_6B_6_3V3 A5E_HVIO_6B_4_3V3
95 A5E_HVIO_6B_3_3V3 GND A5E_HVIO_6B_9_3V3 GND
96 GND +V3P3_HVIO GND +V1P8_HVIO
97 GND GND GND SOM_PRSNT_SEC_2
98 +V12P0 +V12P0 +V12P0 +V12P0
99 GND GND GND GND
100 +V12P0 +V12P0 +V12P0 +V12P0
Level Two Title