Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Quick Start Guide
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Set Up BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. The Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. The Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab 4.3.4.5. The GPIO Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab 4.3.4.3.3. The DP Tab 4.3.4.3.4. The HDMI Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP-2B Tab 4.3.4.4.2. The COMP-3B Tab 4.3.4.4.3. The COMP-3A Tab
4.3.4.5. The GPIO Tab x
4.3.4.5.1. The Push Button Tab 4.3.4.5.2. The Dip Switch Tab 4.3.4.5.3. The I2C Bus Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The System Information 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

B. Developer Resources

Use the following links to check the Altera® website for other related information.
Table 21.   Agilex™ 5 FPGA E-Series 065B Modular Development Kit References
Reference Description
Agilex™ 5 FPGA E-Series 065B Modular Development Kit page Latest board design files, reference designs, and kit installation for Windows* and Linux*.
Rocketboard.org Open-source community website supporting SoC development including Altera and Partner SoC development kit targets and related designs and documentation.
Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Describes the RiscFree* integrated development environment (IDE) for Altera® FPGAs Arm* -based HPS and Nios® V core processors.
Agilex™ 5 FPGA Design Hub The Agilex™ 5 FPGA Design Hub is a comprehensive resource hub that provides a structured approach for developing FPGA-based platforms.
Device Design Guidelines: Agilex™ 5 FPGAs and SoCs Guidelines, recommendations, and a list of factors to consider for designs that use the Agilex™ 5 FPGAs and SoCs.
AN 958: Board Design Guidelines Board design-related resources for Altera®  devices. Its goal is to help you implement successful high-speed PCBs that integrate device(s) and other elements.
Power Management User Guide: Agilex™ 5 FPGAs and SoCs Describes the power-optimization features, power-up and power-down sequences, power distribution network, voltage and temperature monitoring systems, and power optimization techniques for the Agilex™ 5 FPGAs and SoCs.
PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs Provides information for the Agilex™ 5 device family power distribution network (PDN) design guidelines.
FPGA SmartVID SmartVID is a feature on select Altera® FPGAs where the device identifies the optimal voltage that it should be operated at, and provides this information to the power regulator via the PMBus. The term represents Smart Voltage IDentification (SmartVID).
SmartVID Debug Checklist and Voltage Regulator Guidelines Provides the checklist to assist you to rule out the possible causes of configuration failure due to SmartVID.
Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs Agilex™ 5 FPGAs and SoCs support configuration using the following interfaces: Avalon® streaming, JTAG, CvP, and Active Serial (AS) normal and fast modes. This user guide explains the configuration process, the device pins required for configuration, the available configuration schemes, remote system updates, and debugging. This user guide also provides an overview of the secure device manager (SDM) which manages security for the configuration bitstream.
Documentation: Agilex™ 5 Agilex™ 5 device documentation.
Cadence* Capture CIS Schematic Symbols Agilex™ 5 OrCAD symbols.
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