Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Quick Start Guide
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Set Up BTS GUI Running Environment x
4.1.1. Setting Up the Quartus® Prime Software for BTS Operation 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. The Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. The Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab 4.3.4.5. The GPIO Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab 4.3.4.3.3. The DP Tab 4.3.4.3.4. The HDMI Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP-2B Tab 4.3.4.4.2. The COMP-3B Tab 4.3.4.4.3. The COMP-3A Tab
4.3.4.5. The GPIO Tab x
4.3.4.5.1. The Push Button Tab 4.3.4.5.2. The Dip Switch Tab 4.3.4.5.3. The I2C Bus Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The System Information 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Information Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7.3. Carrier Board Primary Connector

Table 18.  Carrier Board Primary Connector (J9)
  A B C D
1 +V1P8_HVIO GND +V3P3_HVIO SOM_PRSNT_PRI_1
2 GND JTAG_TDO_M2C_1V8 GND I2C_SCL2_C2M_B2B_3V3
3 JTAG_TCK_C2M_1V8 JTAG_TDI_C2M_1V8 SOM_RESET_C2M_3V3 I2C_SDA2_C2M_B2B_3V3
4 JTAG_TMS_C2M_1V8 REMOTE_EN_C2M_3V3 INT_N_C2M_1V8 GND
5 SOM_PWR_EN_C2M_3V3 SOM_PWR_OK_M2C_3V3 NSTATUS_M2C_1V8 PMBUS_SDA_C2M_3V3
6 PMBUS_SCL_C2M_3V3 NCONFIG_C2M_1V8 INIT_DONE_M2C_1V8 EN_GROUP2_M2C_3V3
7 GND FAN_PWM_C2M_3V3 CONF_DONE_M2C_1V8 PG_GROUP2_C2M_3V3
8 I2C_SCL1_C2M_B2B_3V3 FAN_TACH_C2M_3V3 MSEL0_C2M_1V8 MSEL1_C2M_1V8
9 I2C_SDA1_C2M_B2B_3V3 GND MSEL2_C2M_1V8 GND
10 GND SFP28_TX_DN GND SFP28_RX_DN
11 GND SFP28_TX_DP GND SFP28_RX_DP
12 ETH0_SGMII_TX_DN GND ETH0_SGMII_RX_DN GND
13 ETH0_SGMII_TX_DP GND ETH0_SGMII_RX_DP GND
14 GND ETH1_SGMII_RX_DN GND SEU_ERROR_M2C_1V8
15 GND ETH1_SGMII_RX_DP GND NC
16 ETH1_SGMII_TX_DN GND ADDR0_M2C_3V3 GND
17 ETH1_SGMII_TX_DP GND ADDR1_M2C_3V3 GND
18 GND CLK_A5E_1C_REC_DN GND CLK_MUX_SI5518_OUT9_OUT12_125M_DN
19 GND CLK_A5E_1C_REC_DP GND CLK_MUX_SI5518_OUT9_OUT12_125M_DP
20 SDI_RX_N GND NC GND
21 SDI_RX_P GND NC GND
22 GND SDI_TX_N GND NC
23 GND SDI_TX_P GND NC
24 A5E_UX_1D_RX_DN GND NC GND
25 A5E_UX_1D_RX_DP GND NC GND
26 GND A5E_UX_1D_TX_DN GND NC
27 GND A5E_UX_1D_TX_DP GND NC
28 CLK_SI5518_OUT8_156.25M_DN GND CLK_A5E_1D_REC_DN GND
29 CLK_SI5518_OUT8_156.25M_DP GND CLK_A5E_1D_REC_DP GND
30 GND FMC_TX2_DN GND FMC_TX3_DN
31 GND FMC_TX2_DP GND FMC_TX3_DP
32 FMC_RX2_DN GND FMC_RX3_DN GND
33 FMC_RX2_DP GND FMC_RX3_DP GND
34 GND FMC_TX0_DN GND FMC_TX1_DN
35 GND FMC_TX0_DP GND FMC_TX1_DP
36 FMC_RX0_DN GND FMC_RX1_DN GND
37 FMC_RX0_DP GND FMC_RX1_DP GND
38 GND CLK_MUX_SI549_FMC_GBTCLK0_DN GND CLK_MUX_SI5518_OUT6_OUT10_156.25M_DN
39 GND CLK_MUX_SI549_FMC_GBTCLK0_DP GND CLK_MUX_SI5518_OUT6_OUT10_156.25M_DP
40 FMC_RX6_DN GND FMC_RX7_DN GND
41 FMC_RX6_DP GND FMC_RX7_DP GND
42 GND FMC_TX4_DN GND FMC_TX7_DN
43 GND FMC_TX4_DP GND FMC_TX7_DP
44 FMC_RX4_DN GND FMC_RX5_DN GND
45 FMC_RX4_DP GND FMC_RX5_DP GND
46 GND FMC_TX5_DN GND FMC_TX6_DN
47 GND FMC_TX5_DP GND FMC_TX6_DP
48 CLK_FMC_GBTCLK1_C_DN GND CLK_MUX_SI5518_OUT5_SI569_DN GND
49 CLK_FMC_GBTCLK1_C_DP GND CLK_MUX_SI5518_OUT5_SI569_DP GND
50 GND LMH1219_LOCK_N_3V3 GND SI569_PWM_VCXO_3_3V3
51 LMH1218_LOCK_3V3 GND SI569_PWM_VCXO_4_3V3 GND
52 LMH1218_LOS_INT_N_3V3 PCIE_EDGE_SMBCLK_3V3 PCIE_EDGE_SMBDAT_3V3 SI569_PWM_VCXO_2_3V3
53 GND BMC_SPI_MISO_3V3 GND SI569_PWM_VCXO_1_3V3
54 BMC_SPI_MOSI_3V3 BMC_SPI_SCLK_3V3 ETH_MDIO_3V3 I2C_FMC_SDA_3V3
55 BMC_UART_TXD_I2C_SDA_3V3 GND ETH_MDC_3V3 GND
56 BMC_UART_RXD_I2C_SCL_3V3 BMC_SPI_CS_3V3 TSN_HVIO_1PPS_OUT_3V3 I2C_FMC_SCL_3V3
57 GND HDMI_RX_HPD_N_1V8 GND TRISYNC_1V8
58 HDMI_TX_HPD_N_1V8 HDMI_TX_CON_SCL_1V8 HDMI_RX_5V_SENSE_1V8 SFP28_INT_1V8
59 HDMI_RX_CON_SDA_1V8 GND MIPI_SPI_CS_1V8 GND
60 HDMI_RX_CON_SCL_1V8 HDMI_TX_CON_SDA_1V8 MIPI_SPI_MISO_1V8 MIPI_XTRIG0_1V8
61 GND MIPI0_FSTROBE_1V8 GND MIPI_XHS0_1V8
62 I2C_HDMI_DP_SDI_SFP_SDA_1V8 MIPI1_FSTROBE_1V8 MIPI_I2C_SDA_SPI_MOSI_1V8 MIPI_XVS0_1V8
63 I2C_HDMI_DP_SDI_SFP_SCL_1V8 GND MIPI_I2C_SCL_SPI_SCLK_1V8 GND
64 FMC_LA_29_1V2_DN FMC_LA_29_1V2_DP FMC_LA_24_1V2_DP FMC_LA_24_1V2_DN
65 GND FMC_LA_11_1V2_DP GND FMC_LA_2_1V2_DP
66 CLK_IO96B_2A_150M_DP FMC_LA_11_1V2_DN FMC_LA_1_1V2_DP FMC_LA_2_1V2_DN
67 CLK_IO96B_2A_150M_DN GND FMC_LA_1_1V2_DN GND
68 MIPI0_DATA1_DP MIPI0_DATA1_DN FMC_LA_10_1V2_DP FMC_LA_10_1V2_DN
69 GND FMC_LA_17_1V2_DP GND FMC_CLK1_M2C_DP
70 MIPI0_DATA0_DP FMC_LA_17_1V2_DN FMC_LA_25_1V2_DP FMC_CLK1_M2C_DN
71 MIPI0_DATA0_DN GND FMC_LA_25_1V2_DN GND
72 FMC_LA_22_1V2_DP FMC_LA_22_1V2_DN FMC_LA_3_1V2_DP FMC_LA_3_1V2_DN
73 GND FMC_LA_15_1V2_DP GND FMC_LA_9_1V2_DP
74 FMC_LA_5_1V2_DP FMC_LA_15_1V2_DN FMC_LA_12_1V2_DP FMC_LA_9_1V2_DN
75 FMC_LA_5_1V2_DN GND FMC_LA_12_1V2_DN GND
76 MIPI0_CLK_DP MIPI0_CLK_DN FMC_LA_14_1V2_DP FMC_LA_14_1V2_DN
77 GND CLK_HDMI_4B_100M_DP GND FMC_LA_23_1V2_DP
78 MIPI0_DATA2_DP CLK_HDMI_4B_100M_DN FMC_LA_16_1V2_DP FMC_LA_23_1V2_DN
79 MIPI0_DATA2_DN GND FMC_LA_16_1V2_DN GND
80 CLK_HDMI_1B_100M_DP CLK_HDMI_1B_100M_DN MIPI0_DATA3_DP MIPI0_DATA3_DN
81 GND FMC_LA_20_1V2_DP GND FMC_LA_26_1V2_DN
82 MIPI1_DATA1_DP FMC_LA_20_1V2_DN NC FMC_LA_26_1V2_DP
83 MIPI1_DATA1_DN GND CLK_SI5518_OUT1_1PPS_1V2 GND
84 FMC_LA_18_1V2_DP FMC_LA_18_1V2_DN FMC_LA_28_1V2_DP FMC_LA_28_1V2_DN
85 GND FMC_LA_30_1V2_DP GND FMC_CLK0_M2C_DP
86 FMC_LA_19_1V2_DP FMC_LA_30_1V2_DN MIPI1_DATA0_DP FMC_CLK0_M2C_DN
87 FMC_LA_19_1V2_DN GND MIPI1_DATA0_DN GND
88 FMC_LA_8_1V2_DP FMC_LA_8_1V2_DN FMC_LA_6_1V2_DP FMC_LA_6_1V2_DN
89 GND MIPI1_CLK_DP GND FMC_LA_7_1V2_DP
90 FMC_LA_21_1V2_DN MIPI1_CLK_DN MIPI1_DATA2_DP FMC_LA_7_1V2_DN
91 FMC_LA_21_1V2_DP GND MIPI1_DATA2_DN GND
92 FMC_LA_0_1V2_DN FMC_LA_0_1V2_DP FMC_LA_4_1V2_DP FMC_LA_4_1V2_DN
93 GND MIPI1_DATA3_DP GND CLK_TOD_156.25M_DP
94 FMC_LA_27_1V2_DN MIPI1_DATA3_DN FMC_LA_13_1V2_DP CLK_TOD_156.25M_DN
95 FMC_LA_27_1V2_DP GND FMC_LA_13_1V2_DN GND
96 SOM_PRSNT_PRI_2 +V1P2_HSIO_2A_M2C GND +V1P2_HSIO_2A_M2C
97 GND GND GND GND
98 +V12P0 +V12P0 +V12P0 +V12P0
99 GND GND GND GND
100 +V12P0 +V12P0 +V12P0 +V12P0
Level Two Title