GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
ID
817660
Date
8/04/2025
Public
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY IP
3.3. Configuring the GTS PMA/FEC Direct PHY IP
3.4. Dynamically Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. Reconfigurable PHY Settings
3.3.4. TX Datapath Options
3.3.5. RX Datapath Options
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.7. FEC Options
3.3.8. PCS Options
3.3.9. Avalon® Memory-Mapped Interface Options
3.3.10. Register Map IP-XACT Support
3.3.11. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.7.1. Clock Ports
3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source
3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2
3.7.4. PMA Fractional Mode
3.7.5. Input Reference Clock Buffer Protection
3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode)
3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode)
3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA
3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
6.1. Instantiating the GTS PMA/FEC Direct PHY IP
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design
6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY IP Example Design
6.7. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design
6.9. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description
6.10. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench
6.11. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.12. Hardware Testing the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit
8.3.2. Programming the Design into an Altera FPGA
8.3.3. Loading the Design to the Transceiver Toolkit
8.3.4. Creating Transceiver Links
8.3.5. Running BER Tests
8.3.6. Running Eye Viewer Tests
8.3.7. Running Link Optimization Tests
3.3.6.4. PMA Configuration Rules for GPON Mode
You can implement the GPON protocol mode with the GTS PMA/FEC Direct PHY IP by using the settings shown below:
- Set the PMA configuration rules parameter to GPON.
- Set the RX Adaptation mode parameter to manual.
- Enable the rx_cdr_fast_freeze_sel port.
- Enable the rx_cdr_freeze port.
To achieve the best RX performance when receiving the burst mode traffic, you must adhere to the following guidelines:
- You must tie the i_rx_cdr_fast_freeze_sel signal to 1’b0.
- You must assert the i_rx_cdr_freeze signal when the burst disappears and deassert the i_rx_cdr_freeze signal when the burst appears.
- During the idle time (no active burst), the differential voltage at the RX should be 0 instead of a positive/negative value. This is to ensure the AC coupling capacitor can quickly charge up to a stable value when the burst arrives.
- You must manually tune the RX EQ parameters: VGA gain, high frequency boost and DFE data tap 1.
Note: When the other parameters are fixed, a smaller RX input voltage swing requires a smaller VGA gain value. A larger RX input voltage swing requires a larger VGA gain value.