GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 8/04/2025
Public
Document Table of Contents

5.6.2. Example Use Case 2

In this example use case, both sides of the device are not fully populated and have the following IPs instantiated:
  • Two GTS Reset Sequencer IP
  • Two GTS PMA/FEC Direct PHY IP
  • Four GTS JESD204C IP
  • One GTS AXI Streaming IP for PCI Express*
  • One HPS USB3.1
Table 88.  GTS Reset Sequencer IP Parameter Settings for Use Case 2
GTS Reset Sequencer IP Parameter Value Selection
# 1 (Left Side) Enable PCIE and/or HPS USB3.1 only design On
Number of Reset Sequencer Lane(s)
Number of Bank(s) 2
# 2 (Right Side) Enable PCIE and/or HPS USB3.1 only design Off
Number of Reset Sequencer Lane(s) 8
Number of Bank(s) 2
The use case also shows you how to use the Enable PCIE and/or HPS USB3.1 only design parameter in a design. In this use case, on the left side of the device, the i_src_rs_req and o_src_rs_grant ports are not needed but o_pma_cu_clk is still needed and cannot be left unconnected.
Figure 84. Example Use Case 2