GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817660
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY IP 4. Implementing the GTS System PLL Clocks IP 5. Implementing the GTS Reset Sequencer IP 6. GTS PMA/FEC Direct PHY IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. CPRI 2.1.1.1.4. GPON 2.1.1.1.5. OTN
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.2.3. Unused PMA Rules x
2.2.3.1. Unused PMA Not Planned for Use in the Future 2.2.3.2. Unused PMA Planned for Use in the Future
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. RX PMA Tuning 2.3.2.5. RX PMA Adaptation Modes
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.3.2.5. RX PMA Adaptation Modes x
2.3.2.5.1. RX Auto Adaptation Mode 2.3.2.5.2. RX Manual Adaptation Mode 2.3.2.5.3. RX Native Adaptation Mode
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLL in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY IP 3.3. Configuring the GTS PMA/FEC Direct PHY IP 3.4. Dynamically Reconfigurable PHY 3.5. Signal and Port Reference 3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.7. Clocking 3.8. Custom Cadence Generation Ports and Logic 3.9. Asserting Reset 3.10. Bonding Implementation 3.11. Configuration Register 3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing 3.13. Configurable Quartus® Prime Software Settings 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Mode and Common Datapath Options 3.3.3. Reconfigurable PHY Settings 3.3.4. TX Datapath Options 3.3.5. RX Datapath Options 3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.7. FEC Options 3.3.8. PCS Options 3.3.9. Avalon® Memory-Mapped Interface Options 3.3.10. Register Map IP-XACT Support 3.3.11. Analog Parameter Options
3.3.4. TX Datapath Options x
3.3.4.1. TX PMA Interface Parameters
3.3.5. RX Datapath Options x
3.3.5.1. RX PMA Interface Parameters
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.6.1. PMA Configuration Rules for SDI Mode 3.3.6.2. PMA Configuration Rules for HDMI Mode 3.3.6.3. PMA Configuration Rules for CPRI Mode 3.3.6.4. PMA Configuration Rules for GPON Mode 3.3.6.5. PMA Configuration Rules for OTN Mode
3.4. Dynamically Reconfigurable PHY x
3.4.1. Clock Generation and Constraints for Multiple Profiles Design
3.5. Signal and Port Reference x
3.5.1. TX and RX Parallel and Serial Interface Signals 3.5.2. TX and RX Reference Clock and Clock Output Interface Signals 3.5.3. Reset Signals 3.5.4. FEC Signals 3.5.5. Custom Cadence Control and Status Signals 3.5.6. RX PMA Status Signals 3.5.7. TX and RX PMA and Core Interface FIFO Signals 3.5.8. Avalon Memory-Mapped Interface Signals
3.7. Clocking x
3.7.1. Clock Ports 3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.7.4. PMA Fractional Mode 3.7.5. Input Reference Clock Buffer Protection 3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
3.7.5. Input Reference Clock Buffer Protection x
3.7.5.1. Reference Clock Buffer Register Information 3.7.5.2. Re-enabling the Reference Clock Buffers
3.8. Custom Cadence Generation Ports and Logic x
3.8.1. Implementing PMA Direct Mode with TX Core FIFO in Elastic Configuration 3.8.2. Enabling the i_tx_cadence_slow_clk_locked Port
3.9. Asserting Reset x
3.9.1. Reset Signal Requirements 3.9.2. Power On Reset Requirements 3.9.3. Reset Signals—Block Level 3.9.4. Run-time Reset Sequence—TX 3.9.5. Run-time Reset Sequence—RX 3.9.6. Run-time Reset Sequence—TX + RX 3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.9.8. TX PLL Lock Loss
3.10. Bonding Implementation x
3.10.1. Bonding Placement Requirements 3.10.2. Multilane RX Simplex Implementation
3.11. Configuration Register x
3.11.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. GTS PMA Register Map 3.11.3. Accessing Configuration Registers 3.11.4. Configuration Registers for the GTS PMA/FEC Direct PHY IP Reconfigurable PHY
3.11.2. GTS PMA Register Map x
3.11.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.11.3. Accessing Configuration Registers x
3.11.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.11.3.2. Accessing GTS PMA Registers
3.12. Configuring the GTS PMA/FEC Direct PHY IP for Hardware Testing x
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP 3.12.2. Using JTAG to Avalon Master Bridge IP
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY IP x
3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.12.2. Using JTAG to Avalon Master Bridge IP x
3.12.2.1. RTL Connection Example for JTAG to Avalon Master Bridge IP
3.13. Configurable Quartus® Prime Software Settings x
3.13.1. Configuring the RX Adaptation Mode and PMA Manual Tuning
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. Direct Register Method 3.14.2. GTS Attribute Access Method
3.14.1. Direct Register Method x
3.14.1.1. Direct Register Method Examples
3.14.2. GTS Attribute Access Method x
3.14.2.1. GTS Attribute Access Method Example 1: Enable or Disable Internal Serial Loopback Mode (RX Auto Adaptation Mode) 3.14.2.2. GTS Attribute Access Method Example 2: Enable or Disable Internal Serial Loopback Mode (RX Manual Adaptation Mode) 3.14.2.3. GTS Attribute Access Method Example 3: Enable or Disable Polarity Inversion of the PMA 3.14.2.4. GTS Attribute Access Method Example 4: Enable PRBS Generator and Checker to Run BER Test
4. Implementing the GTS System PLL Clocks IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer IP General Interface 5.5. GTS Reset Sequencer IP Design Flow 5.6. GTS Reset Sequencer IP Use Cases 5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP
5.6. GTS Reset Sequencer IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY IP 6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design 6.3. GTS PMA/FEC Direct PHY IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY IP Example Design 6.7. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design 6.8. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design 6.9. GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Functional Description 6.10. Simulating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design Testbench 6.11. Compiling the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design 6.12. Hardware Testing the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable PHY Example Design
6.2. Generating the GTS PMA/FEC Direct PHY IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
6.8. Generating the GTS PMA/FEC Direct PHY IP Dynamically Reconfigurable Example Design x
6.8.1. Fast Simulation Support 6.8.2. GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design Directory Structure
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Altera FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY IP
4. Implementing the GTS System PLL Clocks IP
5. Implementing the GTS Reset Sequencer IP
6. GTS PMA/FEC Direct PHY IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.08.04 25.1.1 Made the following changes:
  • Corrected Reed-Solomon FEC code word definition and clause in the Key GTS Transceiver Features table in the GTS Transceiver Overview chapter.
  • Corrected Reed-Solomon FEC code word definition and clause in the Supported FEC Modes and Compliance Specifications and FEC Direct IP Configuration Mode Support tables.
  • Updated the GPON topic with data rates supported.
  • Updated the Channel Placement for PMA Direct Configuration for Bonded Lane Aggregation figure with footnotes.
  • Added new topic, OTN, in the Protocol Support Using PMA Direct Mode section.
  • Updated the RX PMA Tuning topic in the Receiver PMA Architecture section.
  • Added new topic, RX Adaptation Mode, in the Receiver PMA Architecture section.
  • Updated the Reference Clock Source Comparison table in the Reference Clock Network section.
  • Updated the PMA Primary PLL Configuration section with information about OTN.
  • Added a note in the I/O PLLs in HVIO Bank as System PLL topic in the System PLL section.
  • Updated the Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank topic in the System PLL section.
  • Updated the IP Overview section in the Implementing the GTS PMA/FEC Direct PHY IP chapter,
  • Updated the FEC Direct Supported Modes topic in the IP Overview section.
  • Updated the Unsupported PMA/FEC/PCS Modes section with information about OTN.
  • Updated the Direct PHY Operation Mode parameter value setting in the Mode Parameter table.
  • Added the OTN setting for the PMA configuration rules parameter for OTN support in the Common Datapath Options Parameters table.
  • Added a note for the Loopback mode parameter in the TX/RX Common PMA Options Parameters table.
  • Removed the notes in the GTS PMA Transmitter Analog Settings and GTS PMA Receiver Analog Settings tables in the Analog Parameter Options section.
  • Updated the native mode setting description for the RX Adaptation mode parameter and added a new parameter, Selects value of RX termination mode, in the GTS PMA Receiver Analog Settings table.
  • Updated the Enable RX P&N Invert and Enable TX P&N Invert parameter descriptions in the Analog Parameter Options section.
  • Updated the name of the Reconfigurable PHY section to Dynamically Reconfigurable PHY.
  • Updated the description of the o_tx_pll_locked[N-1:0] signal in the TX and RX Reference Clock and Clock Output Interface Signals table.
  • Updated the description of the o_rx_is_lockedtoref[N-1:0] signal in the RX PMA Status Signals table.
  • Removed note about simulation support from the PMA Fractional Mode topic in the Clocking section.
  • Updated the Input Reference Clock Buffer Protection topic in the Clocking section.
  • Added new topic, Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status, in the Clocking section.
  • Updated the tx_cadence_fast_clk and tx_cadence_slow_clk connections table in the Custom Cadence Generation Ports and Logic section.
  • Added new topic, Implementing PMA Direct Mode with TX Core FIFO in Elastic Configuration, in the Custom Cadence Generation Ports and Logic section.
  • Updated the TX PLL Lock Loss topic and removed the TX PLL Lock Loss Auto Recovery (Soft CSR Enabled) topic in the Asserting Reset section.
  • Removed the footnotes in the Configurable Quartus® Prime Software Settings section.
  • Added new topic, Configuring the RX Adaptation Mode and PMA Manual Tuning, with information about Auto Adaptation Mode and Manual Adaptation Mode in the Configurable Quartus® Prime Software Settings section.
  • Removed some footnotes in the Direct Register Method Examples section.
  • Updated the GTS Attribute Access Data Value 1 table in the GTS Attribute Access Method section.
  • Added new topic, GTS Attribute Access Method Example 2, in the GTS Attribute Access Method section.
  • Updated the overview description for the Implementing the GTS System PLL Clocks IP section.
  • Updated the Example Design Options for the Reconfigurable PHY table in the GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design section.
  • Updated step 1 and the figures in the Generating the GTS PMA/FEC Direct PHY Reconfigurable Example Design section.
  • Updated the Clocking and Datapath Tool section with datapath clocking mode information.
  • Updated the IP name instances from Intel FPGA IP to IP throughout the user guide.
2025.04.07 25.1 Made the following changes:
  • Updated the Hard IP Configurations Supported with PMA table in the Building Blocks section.
  • Removed the OTN and DisplayPort topics from the Protocol Support Using PMA Direct Mode section.
  • Removed OTN support from the PCS topic in the Building Blocks section.
  • Updated the figures in the Hard IP Rules section with an additional note.
  • Corrected the device in the Unused PMA Not Planned for Use in the Future topic in the Unused PMA Rules section.
  • Updated the RX termination information in the Receiver Buffer and Equalizer section.
  • Updated the Reference Clock Network for Devices with Multiple GTS Transceiver Banks on a Side figure and the Reference Clock Source Comparison table in the Reference Clock Network section.
  • Updated the Reference Clock Network for Devices with a Single GTS Transceiver Bank on a Side figure in the Single GTS Transceiver Bank Device section.
  • Updated the I/O PLLs in HVIO Bank as System PLL section with additional details about the HVIO banks adjacent to the transceiver bank and reference clocks for the I/O PLLs.
  • Updated the System PLL with HVIO Reference Clock section with HVIO bank information.
  • Updated the Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank section with additional information about the shared banks.
  • Updated the PMA Direct Mode with PMA Clocking figure for TX/RX core interface FIFO elastic mode support in the IP Overview section.
  • Updated the PMA Direct Mode Support table for TX/RX core interface FIFO elastic mode support in the PMA Direct Supported Modes section.
  • Removed mention of OTN and DisplayPort in the Unsupported PMA/FEC/PCS Modes section.
  • Updated the Common Datapath Options section name to Mode and Common Datapath Options.
  • Added a new parameter for Direct PHY operation mode in the Mode Parameter table.
  • Added support for GPON and removed support for OTN and DisplayPort from the PMA configuration rules parameter in the Common Datapath Options Parameters table.
  • Added a note for the Enable refclock to core parameter in the Common Datapath Options Parameters table.
  • Added reverse parallel setting for the Loopback mode parameter in the TX/RX Common PMA Options Parameters table.
  • Added a new section Reconfigurable PHY Settings with information about the Reconfigurable PHY parameter settings.
  • Added the PRBS generator mode parameter and a note for the Enable TX PLL cascade mode parameter in the TX Datapath Options Parameters table.
  • Added the PRBS monitor mode parameter in the RX Datapath Options Parameters table.
  • Added the PMA Configuration Rules for GPON Mode topic and removed the PMA Configuration Rules for DisplayPort Mode topic in the PMA Configuration Rules for Specific Protocol Mode Implementations section.
  • Updated the GTS PMA Receiver Analog Settings table with several changes: Added native setting for the RX Adaptation mode parameter, removed the Selects value of RX termination mode parameter, updated the default values for the RX equalization parameters, and removed the Enable VSR mode parameter.
  • Added a new section Reconfigurable PHY with information about the Reconfigurable PHY profile settings.
  • Updated the TX and RX Reference Clock and Clock Output Interface Signals table with additional information for the i_tx_pll_refclk_p[N-1:0] signal.
  • Updated the RX PMA Status Signals table with additional signals for the GPON protocol.
  • Updated Reset Signals table and added a new signal o_refclk_bus_out.
  • Updated the PMA Direct Mode Parallel Data Calculations table with information about PMA Direct mode with PMA clocking in elastic mode in the Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath section.
  • Updated the Example of Bit Mapping of TX Parallel Data Bits for PMA Direct Mode with PMA Width = 32 table with information about PMA Direct mode with PMA clocking in elastic mode.
  • Updated the parallel data information in the PCS Direct Mode — IEEE MII Interface Parallel Data Calculations table for MSB bit 37.
  • Updated the parallel data information in the PCS Direct Mode — IEEE_FLEXE_66/PCS66 Parallel Data Calculations table for MSB bit 37.
  • Updated the description in the TX and RX Parallel Data to IEEE_FLEXE_66/PCS66 Mapping Signals for PCS Direct Mode table for PCS66 mode data.
  • Updated information in step 1 in the Re-enabling the Reference Clock Buffers section to determine if a reference clock buffer has been turned off.
  • Updated the Custom Cadence Generation Ports and Logic section with information about PMA Direct mode with PMA clocking in elastic mode.
  • Removed support for DIV 68 for FEC Direct mode in the tx_cadence_fast_clk and tx_cadence_slow_clk connections table.
  • Updated the note in the RX Data Loss/CDR Lock Loss (Auto-Recovery) section for RX adaptation mode.
  • Updated the Example 1: Accessing PMA Physical Lane Information topic in the Accessing GTS PMA Registers section.
  • Removed the VSR Mode settings from the Configurable Quartus® Prime Software Settings section.
  • Added steps for Reverse Parallel Loopback setting in the Direct Register Method Examples section.
  • Added setting for RX to TX parallel loopback in the GTS Attribute Access Data Value 1 table in the GTS Attribute Access Method section.
  • Added a note in the Polarity Setup column in the GTS Attribute Access Data Value 1 table in the GTS Attribute Access Method section.
  • Removed the VSR Mode column from the GTS Attribute Access Data Value 3 table in the GTS Attribute Access Method section.
  • Updated the Logic Usage of the GTS Reset Sequencer IP (For Agilex™ 5 E-Series and D-Series Devices) table.
  • Updated the GTS Reset Sequencer IP Port List table with two new ports: i_refclk_bus_out and o_shoreline_refclk_fail_stat.
  • Updated the GTS Reset Sequencer IP General Interface figure.
  • Added new section Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer IP in the Implementing the GTS Reset Sequencer IP chapter.
  • Updated the GTS PMA/FEC Direct PHY IP Example Design Functional Description section and removed the separate PCS test wrap description.
  • Added new sub-sections Generating the GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design, GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design Functional Description, Simulating the GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design Testbench, Compiling the GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design, and Hardware Testing the GTS PMA/FEC Direct PHY IP Reconfigurable PHY Example Design with information about the Reconfigurable PHY example design.
2025.01.24 24.3.1 Made the following changes:
  • Added the OTN topic in the Protocol Support Using PMA Direct Mode section.
  • Updated the independent TX simple and RX simplex information in the Design Rules Associated With Specific Use Scenarios table.
  • Updated the Receiver Buffer and Equalizer section with information about cut-off frequency in bullet 2.
  • Updated the Unused PMA Rules section with two new topics Unused PMA Not Planned for Use in the Future and Unused PMA Planned for Use in the Future.
  • Updated the PCS Direct Supported Modes table in the PCS Architecture section.
  • Updated the FEC loopback mode section with the corrected loopback mode register.
  • Updated the Reference Clock Network section with information about clocks that can be routed to the FPGA core.
  • Updated the Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank section with information about the HVIO bank location.
  • Updated information in the System PLL Clock for FPGA Core topic.
  • Updated the TX Deskew Function topic for clarity.
  • Updated the FEC Supported Modes section with information about the simplex mode support.
  • Updated the PCS Supported Modes section with footnote about the hardware testing support.
  • Updated the Unsupported PMA/FEC/PCS Modes section with information about the RX simplex mode support.
  • Updated the Number of PMA lanes parameter values and description in the Common Datapath Options Parameters table.
  • Added note for Enable rx_set_locktoref port parameter in the RX Datapath Options Parameters table.
  • Updated the PMA Configuration Rules for HDMI Mode and PMA Configuration Rules for DisplayPort Mode topics with information about multilane RX simplex mode requirements.
  • Updated note for the Enable TX P&N Invert and Enable RX P&N Invert parameters in the Analog Parameter Options section.
  • Added Enable VSR mode parameter GTS PMA Receiver Analog Settings table.
  • Added note for i_reconfig_reset signal in the Avalon® Memory-Mapped Interface Signals table.
  • Added new section Input Reference Clock Buffer Protection with two topics Reference Clock Buffer Register Information and Re-enabling the Clock Buffers.
  • Added new topic TX PLL Lock Loss Auto Recovery (Soft CSR Enabled) in the Asserting Reset section.
  • Added new topic Multilane RX Simplex Implementation in the Bonding Implementation section.
  • Updated the Configurable Quartus® Prime Software Settings section with information about TX Invert, RX Invert, Manual Tuning, and VSR Mode qsf settings.
  • Updated the Direct Register Method Examples topic with information about Measuring the Bit Error Rate.
  • Updated the GTS Attribute Access Data Value 1 table and added two new tables in the GTS Attribute Access Method section.
  • Added new topic GTS Attribute Access Method Example 3 in the GTS Attribute Access Method section.
  • Updated the GTS System PLL Clock Intel FPGA IP Parameters table with the FABRIC_USE_CASE, Output frequency C1 enable and Output frequency C1 parameters.
  • Updated the i_refclk_ready port description in the GTS System PLL Clock Intel FPGA IP Port List table.
  • Added new topic Example Flow to Indicate System PLL Reference Clock is Ready in the Guidelines to Indicate System PLL Reference Clock is Ready section.
  • Added note for internal serial loopback script in the Hardware Testing the GTS PMA/FEC Direct PHY FPGA IP Example Design section.
2024.10.07 24.3 Made the following changes:
  • Corrected the Key GTS Transceiver Features table with the Ethernet Technology Consortium (ETC) FEC naming in the GTS Transceiver Overview chapter.
  • Added new figure GTS Transceiver Design Flow in the GTS Transceiver Overview chapter.
  • Added figure GTS Transceiver Bank Layout for E-Series FPGAs with 8 GTS Transceivers in the Building Blocks section.
  • Updated note about FEC support for PCS Direct mode in the Hard IP Configurations Supported with PMA table.
  • Added new section Protocol Support using PMA Direct Mode with sub-sections for SDI, HDMI, DisplayPort and CPRI protocol support information.
  • Updated the A5E 028 device power down support bank for the M16A package in the Selected E-Series GTS Transceiver Banks that Support Power Down table.
  • Updated the Data Pattern Generator and Verifier section with new information about the built-in PRBS generator and verifier.
  • Updated the PCS Architecture section with IEEE 802.3 compliant Clause 107 support and updated naming for the IEEE MII interface.
  • Corrected the Supported FEC Modes and Compliance Specifications table with the Ethernet Technology Consortium (ETC) FEC naming in the Forward Error Correction (FEC) Architecture section.
  • Added bonding support for the x6 and x8 modes for PCS Direct mode in the Bonding Architecture section.
  • Corrected the Ethernet Technology Consortium (ETC) FEC naming in the FEC Direct Supported Modes section.
  • Updated the PCS Direct Supported Modes section with simplex and duplex support and updated naming for the IEEE MII interface.
  • Updated supported modes in the Unsupported PMA/FEC/PCS Modes section.
  • Updated the Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP section with Riviera-PRO* simulator support.
  • Removed note from the Provide separate interface for each PMA parameter in the Common Datapath Options section.
  • Added new section PMA Configuration Rules for Specific Protocol Mode Implementation with sub-sections for PMA Configuration Rules for SDI Mode, PMA Configuration Rules for HDMI Mode, PMA Configuration Rules for DP Mode and PMA Configuration Rules for CPRI Mode protocol modes.
  • Corrected the Ethernet Technology Consortium (ETC) FEC naming in the FEC Options section.
  • Updated naming for the IEEE MII interface in the PCS Options section.
  • Removed note from the Enable separate Avalon interface per PMA parameter in the Avalon® Memory-Mapped Interface Options section.
  • Updated the Analog Parameter Options in Parameter Editor figure in the Analog Parameter Options section.
  • Removed signals o_tx_am_gen_start and i_tx_am_gen_2x_ack from the Reset Signals table.
  • Removed the PCS Direct Signals: IEEE and PCS Direct Signals: IEEE_FLEXE_66/PCS66 topics from the Signal and Port Reference section.
  • Added new tables TX and RX Parallel Data to IEEE MII Port Mapping Signals for PCS Direct Mode and TX and RX Parallel Data to IEEE_FLEXE_66/PCS66 Mapping Signals for PCS Direct Mode in the Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath section.
  • Removed signals o_tx_am_gen_start and i_tx_am_gen_2x_ack from the Reset Signal Requirements section.
  • Added note in the Run-time Reset Sequence—TX topic about RS-FEC mode support.
  • Removed the Run-time Reset Sequence—TX with FEC topic from the Reset Signal Requirements section.
  • Added note about using the TX Equalizer Tool in the TX Equalizer Co-efficients topic in the Direct Register Method Examples section.
  • Added Riviera-PRO* script location in the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure section.
  • Added Riviera-PRO* script run command in the Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench section.
  • Added information about modifying the example design pin assignments in the Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design section.
2024.07.08 24.2 Made the following changes:
  • Added a note about restricted support for Agilex™ 5 D-Series FPGAs in the GTS Transceiver Overview section.
  • Updated the Agilex™ 5 D-Series FPGA package information in figures in the Building Blocks section.
  • Added new table with the Agilex™ 5 D-Series FPGA power down information in the Unused PMA Rules section.
  • Updated the System PLL Clock Network figure in the System PLL section.
  • Added new section Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank with information about shared clocking resources.
  • Clarified information in the I/O PLLs in HVIO Bank as System PLL section.
  • Added new section PCS Architecture with information about PCS direct modes.
  • Updated information in the FEC Loopback Mode section.
  • Added information about PCS direct mode in the Bonding Architecture section.
  • Updated the IP Overview section with the PCS direct mode information.
  • Updated the Preset IP Parameter Settings section with the PCS direct mode preset.
  • Updated PMA data rate parameter setting values and default value in description in the Common Datapath Options section.
  • Added new section PCS Options with information about the PCS direct parameter settings.
  • Updated the Enable readdatavalid port on Avalon® interface parameter setting in the Avalon® Memory-Mapped Interface Options section.
  • Added new section Register Map IP-XACT Support with information about the register map support in IP-XACT.
  • Added new section Analog Parameter Options with information about the RX and TX Analog parameter settings.
  • Added additional description for the i_tx_pll_refclk_p[N-1:0] and i_rx_cdr_refclk_p[N-1:0] signals in the TX and RX Reference Clock and Clock Output Interface Signals table.
  • Added PCS direct mode parallel data calculations in the Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath section.
  • Updated the RX Manual Tuning description in the Configurable Software Settings section.
  • Updated the register map addresses for TX equalization in Logical Avalon Memory-Mapped Port Indexing and Direct Register Method Examples sections.
  • Updated the GTS Attribute Access Data Value 1 table with TX to RX parallel loopback data field value.
  • Updated the GTS System PLL Clock Intel FPGA IP Parameters and Mode of System PLL - System PLL Reference Clock and Output Frequencies tables with PCIE_FREQ_500 value setting.
  • Updated the Guidelines for GTS System PLL Clocks Intel FPGA IP Usage section with PCIe* compliance information.
  • Updated the Implementing the GTS Reset Sequencer Intel FPGA IP chapter introduction.
  • Updated the GTS Reset Sequencer Intel FPGA IP Design Flow section with additional information.
  • Updated supported simulator from VCS* to VCS* MX in several sections.
  • Updated the Example Design Options table with PCS direct mode and several 28.1 Gbps options.
  • Updated the Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design section with development kit board selection information.
  • Updated the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description section with the PCS direct mode information.
  • Added note in the Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench section about VCS* MX waveform generation.
  • Added note in the Modifying the Example Design and Performing Simulation section about soft reset controller simulation model.
  • Added new section Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design.
  • Updated the Running Eye Viewer Tests section with information about the Eye Width measurements.
  • Updated the Running Link Optimization Tests section with information about the Eye Width measurements.
2024.04.01 24.1 Initial release.
Level Two Title