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1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Micro Processor Unit (MPU)
4. Application Processor Subsystem
5. Peripheral Subsystem
6. System Manager
7. Clock Manager
8. Reset Manager
9. Power Management
10. Address Map
11. Bridges
12. Interfaces
13. System Interconnect and Firewalls
14. Error Checking and Correction Controller
15. CoreSight Debug and Trace
16. HPS Register Map
A. Appendix
1.1. Introduction to the HPS Revision History
1.2. MPU Revision History
1.3. CCU Revision History
1.4. GIC Revision History
1.5. SMMU Revision History
1.6. On-Chip RAM Revision History
1.7. EMAC Revision History
1.8. DMA Controller Revision History
1.9. NAND Flash Controller Revision History
1.10. SD/eMMC Revision History
1.11. Combo DLL PHY Revision History
1.12. USB 3.1 Gen1 Controller Revision History
1.13. USB 2.0 OTG Controller Revision History
1.14. I3C Controller Revision History
1.15. I2C Controller Revision History
1.16. SPI Controller Revision History
1.17. Timers Revision History
1.18. Watchdog Timers Revision History
1.19. UART Controller Revision History
1.20. GPIO Revision History
1.21. I/O Pin Multiplexing Revision History
1.22. System Manager Revision History
1.23. Clock Manager Revision History
1.24. Reset Manager Revision History
1.25. Power Management Revision History
1.26. Bridges Revision History
1.27. HPS Mailbox Revision History
1.28. MPFE and MPFE-lite Revision History
1.29. EMAC GMII through FPGA Fabric Revision History
1.30. System Interconnect and Firewalls Revision History
1.31. ECC Controller Revision History
1.32. CoreSight* Debug and Trace Revision History
1.33. HPS Register Map Revision History
1.34. Booting and Configuration Revision History
1.35. HPS Use of SDM QSPI Controller Revision History
1.36. Security Revision History
2.3.1. HPS Block Diagram
2.3.2. MPU Features
2.3.3. Application Processor Subsystem
2.3.4. Peripheral Subsystem
2.3.5. System Manager Features
2.3.6. Clock Manager Features
2.3.7. Reset Manager Features
2.3.8. Bridges Features
2.3.9. System Interconnect and Firewalls Features
2.3.10. ECC Controller Features
2.3.11. CoreSight Debug and Trace Features
2.3.4.1. EMAC Features
2.3.4.2. DMA Controller Features
2.3.4.3. NAND Flash Controller Features
2.3.4.4. Combo DLL PHY Features
2.3.4.5. USB 3.1 Gen1 Controller Features
2.3.4.6. USB 2.0 OTG Controller Features
2.3.4.7. I3C Controller Features
2.3.4.8. I2C Controller Features
2.3.4.9. SPI Controller Features
2.3.4.10. Timers Features
2.3.4.11. Watchdog Timers Features
2.3.4.12. UART Controller Features
2.3.4.13. GPIO Features
2.3.4.14. I/O Pin Multiplexing Features
3.1. MPU Differences Among Intel SoC Device Families
3.2. MPU Use Cases
3.3. MPU Features
3.4. MPU System Integration
3.5. MPU Arm* Cortex* -A76 Core
3.6. MPU Arm* Cortex* -A55 Core
3.7. MPU Arm* DynamIQ Shared Unit
3.8. MPU Clock Domains
3.9. MPU Reset Domains
3.10. MPU Power Domains
3.11. MPU Address Map and Register Definitions
3.5.3.1. Cortex* -A76 Core Configuration
3.5.3.2. Exception Levels
3.5.3.3. Virtualization
3.5.3.4. Memory Management Unit
3.5.3.5. Level 1 Memory System
3.5.3.6. Level 2 Memory System
3.5.3.7. Generic Interrupt Controller CPU Interface
3.5.3.8. Advanced Single Instruction Multiple Data and Floating Point Support
3.5.3.9. Cryptographic Extensions
3.5.3.10. Generic Timer
3.5.3.11. Cache Protection
3.5.3.12. Debug
3.6.3.1. Cortex* -A55 Core Configuration
3.6.3.2. Exception Levels
3.6.3.3. Virtualization
3.6.3.4. Memory Management Unit
3.6.3.5. Level 1 Memory System
3.6.3.6. Level 2 Memory System
3.6.3.7. Generic Interrupt Controller CPU Interface
3.6.3.8. Data Processing Unit
3.6.3.9. Generic Timer
3.6.3.10. Cache Protection
3.6.3.11. Debug
4.1.5.1. Block Diagram
4.1.5.2. Ports
4.1.5.3. Cache Coherency Protocol
4.1.5.4. Addressing and Memory Regions
4.1.5.5. Connectivity
4.1.5.6. Snoop Filters
4.1.5.7. System Memory Cache
4.1.5.8. Credits and Resources
4.1.5.9. Quality of Service
4.1.5.10. Storage Protection
4.1.5.11. Exclusive Monitors
4.1.5.12. Firewall and Security
4.1.5.13. Interrupts
4.1.5.14. Clocks
4.1.5.15. Resets
4.1.5.16. Power Management
4.1.5.17. Shutdown of Interfaces
4.1.5.18. Error Handling
4.1.5.19. CCU Restrictions
4.1.5.2.1. DSU CHI-B Initiator Port
4.1.5.2.2. F2H ACE-Lite Initiator Port
4.1.5.2.3. GIC_M ACE-lite Initiator Port
4.1.5.2.4. TCU Ace-lite+DVM Initiator Port
4.1.5.2.5. CCU_IOM ACE-Lite Initiator Port
4.1.5.2.6. CCU_DMI0, CCU_DMI1 1AXI4 Target Ports
4.1.5.2.7. CCU_IOS AXI Target Port
4.1.5.2.8. MPFE CSR AXI Target Port
4.1.5.2.9. GIC AXI Target Port
4.1.5.2.10. OCRAM AXI Target Port
4.3.1. SMMU Differences Among Intel SoC Device Families
4.3.2. SMMU Use Cases
4.3.3. SMMU Features
4.3.4. SMMU System Integration
4.3.5. SMMU Signal Description
4.3.6. SMMU Functional Description
4.3.7. SMMU Programming Model
4.3.8. SMMU Address Map and Register Definitions
4.3.9. SMMU Design Guidelines and Examples
4.3.7.1. Initializing the SMMU
4.3.7.2. Assigning Stream IDs
4.3.7.3. Allocating the Command Queue
4.3.7.4. Allocating the Event Queue
4.3.7.5. Configuring the Stream Table
4.3.7.6. Initializing the Command Queue
4.3.7.7. Initializing the Event Queue
4.3.7.8. Invalidate TLBs and Configuration caches
4.3.7.9. Create Context Descriptor
4.3.7.10. Creating Stream Table Entry
4.3.7.11. Enabling the SMMU
5.1. Ethernet Media Access Controller
5.2. DMA Controller
5.3. NAND Flash Controller
5.4. SD/eMMC Host Controller
5.5. Combo DLL PHY
5.6. USB 3.1 Gen1 Controller
5.7. USB 2.0 OTG Controller
5.8. I3C Controller
5.9. I2C Controller
5.10. SPI Controller
5.11. Timers
5.12. Watchdog Timers
5.13. UART Controller
5.14. General-Purpose I/O Interface (GPIO)
5.15. Hard Processor System I/O Pin Multiplexing
5.1.1. EMAC Differences Among Intel SoC Device Families
5.1.2. EMAC Use Cases
5.1.3. EMAC Features
5.1.4. EMAC System Integration
5.1.5. EMAC Signal Description and Interfaces
5.1.6. EMAC Functional Description
5.1.7. EMAC Programming Model
5.1.8. EMAC Address Map and Register Definitions
5.1.9. EMAC Design Guidelines and Examples
5.1.6.1. External Memory
5.1.6.2. DMA Controller
5.1.6.3. Descriptor
5.1.6.4. Checksum Offload Engine (COE)
5.1.6.5. TCP Segmentation Offload
5.1.6.6. Packet Filtering
5.1.6.7. Management Counter
5.1.6.8. Flow Control
5.1.6.9. IEEE 1588-2008 Advanced Timestamp
5.1.6.10. TSN Features
5.1.6.11. SMTG Hub Time of Day Synchronization
5.1.6.12. Clocks
5.1.6.13. Resets
5.1.6.14. Interrupts
5.1.6.2.1. Application Bus Burst Access
5.1.6.2.2. Application Data Buffer Alignment
5.1.6.2.3. Buffer Size Calculations
5.1.6.2.4. DMA Descriptor Fetch Operation
5.1.6.2.5. DMA TX Data Transfer Operation
5.1.6.2.6. DMA RX Data Transfer Operation
5.1.6.2.7. DMA Descriptor Write-Back Operation
5.1.6.2.8. DMA Start/Stop Operation
5.1.6.2.9. Memory Cache Size Requirements
5.1.6.2.10. Memory Cache Access Arbitration
5.1.6.2.11. DMA Error Handling
5.1.7.1. System Level EMAC configurable Registers
5.1.7.2. EMAC HPS Interface Initialization
5.1.7.3. EMAC FPGA Interface Initialization
5.1.7.4. DMA Initialization
5.1.7.5. EMAC Initialization and Configuration
5.1.7.6. Performing Normal Receive and Transmit Operation
5.1.7.7. Stopping and Starting Transmission
5.1.7.8. Reconfiguring the DMA Registers
5.1.7.9. Switching to a New Descriptor List in the Receive DMA
5.1.7.10. Handling Bus Errors and Recovery
5.1.7.11. Setting up TCP Segmentation Offload
5.1.7.12. Setting up VLAN Filtering on Receive
5.1.7.13. Setting up Extended VLAN Filtering
5.1.7.14. Setting up the L3-L4 Filtering
5.1.7.15. Programming the SMTG Hub
5.1.7.16. Setting up the IEEE 1588 PTP Timestamping
5.1.7.17. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
5.1.7.18. Programming the GCL and GCL Linked Registers
5.1.7.19. Programming Guidelines for EST
5.1.7.20. Enabling the Frame Preemption Function
5.1.7.21. Setting up the Time-Based Scheduling Function
5.3.1. NAND Flash Controller Differences Among Intel SoC Device Families
5.3.2. NAND Flash Controller Use Cases
5.3.3. NAND Flash Controller Features
5.3.4. NAND Flash Controller System Integration
5.3.5. NAND Flash Controller Signal Description
5.3.6. NAND Flash Controller Functional Description
5.3.7. NAND Flash Controller Programming Model
5.3.8. NAND Flash Controller Address Map and Register Definitions
5.3.6.1. Block Diagram
5.3.6.2. Initialization Protocol (Device Discovery)
5.3.6.3. NAND Flash Addressing and Data Layout
5.3.6.4. Command Engine Functionality
5.3.6.5. ECC Engine Functionality
5.3.6.6. Control Data Mechanism
5.3.6.7. Remapping Mechanism
5.3.6.8. Write Protection Mechanism
5.3.6.9. Error and Special Scenarios Handling
5.3.6.10. Controller Fixed Parameters and Clock Frequencies Supported
5.3.7.1. NAND Controller Registers Programming Model
5.3.7.2. Status Polling Configuration
5.3.7.3. Device Layout Configuration
5.3.7.4. Configure Multiplane and Cache Operations
5.3.7.5. ECC Enabling
5.3.7.6. Interrupts Configuration
5.3.7.7. Configuring Timing Registers
5.3.7.8. Switch from SDR to DDR Operation Mode
5.3.7.9. Switch from DDR to SDR Operation Mode
5.3.7.10. Slave DMA Programming
5.3.7.11. Data Pre-Fetching Mechanism
5.3.7.12. Data Integrity Mechanism
5.3.7.13. Enabling pSLC Mode for the TLC Devices
5.4.1. SD/eMMC Differences Among Intel SoC Device Families
5.4.2. SD/eMMC Use Cases
5.4.3. SD/eMMC Features
5.4.4. SD/eMMC System Integration
5.4.5. SD/eMMC Signal Description
5.4.6. SD/eMMC Functional Description
5.4.7. SD/eMMC Programming Model
5.4.8. SD/eMMC Address Map and Register Definitions
5.4.9. SD/eMMC Design Guidelines and Examples
5.4.6.1.1. Bus Interface Unit
5.4.6.1.2. Reset Control Module
5.4.6.1.3. Synchronization Module
5.4.6.1.4. Response Module
5.4.6.1.5. FIFO Interface Unit
5.4.6.1.6. Card Interface Unit
5.4.6.1.7. System Requester Interface
5.4.6.1.8. System Manager Interface
5.4.6.1.9. Host Settings Interface
5.4.6.1.10. Command Queue Settings
5.5.1. Combo DLL PHY Differences Among Intel SoC Device Families
5.5.2. Combo DLL PHY Use Cases
5.5.3. Combo DLL PHY Features
5.5.4. Combo DLL PHY System Integration
5.5.5. Combo DLL PHY Signal Description
5.5.6. Combo DLL PHY Functional Description
5.5.7. Combo DLL PHY Programming Model
5.5.8. Combo DLL PHY Address Map and Register Definitions
5.6.1. USB 3.1 Gen1 Controller Differences Among Intel SoC Device Families
5.6.2. USB 3.1 Gen1 Controller Use Cases
5.6.3. USB 3.1 Gen1 Controller Features
5.6.4. USB 3.1 Gen1 Controller System Integration
5.6.5. USB 3.1 Gen1 Controller Functional Description
5.6.6. USB 3.1 Gen1 Controller Programming Model
5.6.7. USB 3.1 Gen1 Controller Address Map and Register Definitions
5.6.8. USB 3.1 Gen1 Controller Design Guidelines and Examples
5.6.5.1. Manager Interface
5.6.5.2. AHB Subordinate Interface
5.6.5.3. Application interface Unit
5.6.5.4. Bus Management Unit
5.6.5.5. Packet FIFO Controller
5.6.5.6. RAM
5.6.5.7. MAC
5.6.5.8. DMA
5.6.5.9. Loopback
5.6.5.10. PHY Interfaces
5.6.5.11. USB 3.1 Gen1 Controller Clocks
5.6.5.12. USB 3.1 Gen1 Controller Resets
5.6.6.2.1. Device Power-on or Soft Reset
5.6.6.2.2. Initialization on USB Reset
5.6.6.2.3. Initialization on Connect Done
5.6.6.2.4. Initialization on SetAddress Request
5.6.6.2.5. Initialization on SetConfiguration or SetInterface Request
5.6.6.2.6. Agilex 5 Programming Model
5.6.6.2.7. Controller as Host
5.7.1. USB 2.0 OTG Controller Differences Among Intel SoC Device Families
5.7.2. USB 2.0 OTG Controller Use Cases
5.7.3. USB 2.0 OTG Controller Features
5.7.4. USB 2.0 OTG Controller System Integration
5.7.5. USB 2.0 OTG Controller Functional Description
5.7.6. USB 2.0 OTG Controller Programming Model
5.7.7. USB 2.0 OTG Controller Address Map and Register Definitions
5.8.1. I3C Controller Differences Among Intel SoC Device Families
5.8.2. I3C Controller Use Cases
5.8.3. I3C Controller Features
5.8.4. I3C Controller System Integration
5.8.5. I3C Controller Signal Description
5.8.6. I3C Controller Functional Description
5.8.7. I3C Controller Programming Model
5.8.8. I3C Controller Address Map and Register Definitions
5.8.9. I3C Controller Design Guidelines and Examples
5.8.6.5.1. Dynamic Address Assignment (DAA)
5.8.6.5.2. In-Band Interrupt (IBI) Detection and Handling
5.8.6.5.3. I3C Slave Interrupt Request (SIR)
5.8.6.5.4. Disabling I3C Master
5.8.6.5.5. Aborting Transfers of I3C Master
5.8.6.5.6. I3C Master Request (MR)
5.8.6.5.7. Master Command Data Structures
5.8.6.5.8. Response Data Structure
5.8.6.5.9. Operation Modes of I3C Controller
5.8.6.5.10. SCL Generation and Timings Based on Bus Configuration
5.8.6.5.11. Derivation of I3C/I2C Timing Parameters from Timing Registers
5.8.6.5.12. Error Detection
5.8.6.5.13. Defining Byte Support
5.8.6.5.14. Broadcast CCCs in I2C Speed
5.8.6.5.15. BUS RESET Generation DMA Controller Interface
5.8.6.5.9.1. Single Data Rate (SDR) Transfers in Master Mode
5.8.6.5.9.2. Broadcast CCC Write Transfers
5.8.6.5.9.3. Directed Write and Read Transfers
5.8.6.5.9.4. Directed CCC Transfer Targeted to Multiple Slaves
5.8.6.5.9.5. I3C Private Write or Read Transfers
5.8.6.5.9.6. I2C Private Write or Read Transfers
5.8.6.5.9.7. Implication of TX-FIFO Empty and RX-FIFO Full Conditions
5.8.6.5.9.8. Implication of TOC and ROC Bit Settings for SDR Transfers
5.8.6.6.1. Description of the Slave Role in I3C
5.8.6.6.2. I3C versus I2C Role Selection
5.8.6.6.3. Slave Role Related Registers
5.8.6.6.4. Handling Address Assignment
5.8.6.6.5. CCC Transfers with I3C Slave
5.8.6.6.6. Private Data Transfers
5.8.6.6.7. Handling Private Transmit (Master Read) Transfers
5.8.6.6.8. Slave Interrupt Request Generation
5.8.6.6.9. Master Request Generation
5.8.6.6.10. Disabling I3C Slave
5.8.6.6.11. Data Structure in I3C Slave
5.8.7.6.1. Private Receive (Master Write) Transfers in Slave Mode
5.8.7.6.2. Private Transmit (Master Read) Transfers in Slave Mode
5.8.7.6.3. Programming Flow for Generating Slave Interrupt Request
5.8.7.6.4. Programming Flow for Generating Master Request
5.8.7.6.5. Programming Flow to Prepare the Controller to Switch to Master Mode
5.8.7.6.6. Command Pipeline and Aggregation of Response Queue Threshold Interrupt
5.8.7.6.7. Error Recovery Flow
5.8.7.6.8. CCC Updated Interrupt Flow
5.8.7.6.9. Flow for Disable and TX/RX/CMD/Response Queue Reset
5.9.1. I2C Controller Differences Among Intel SoC Device Families
5.9.2. I2C Controller Use Cases
5.9.3. I2C Controller Features
5.9.4. I2C Controller System Integration
5.9.5. I2C Controller Signal Description
5.9.6. I2C Controller Functional Description
5.9.7. I2C Controller Programming Model
5.9.8. I2C Controller Address Map and Register Definitions
5.9.9. I2C Controller Design Guidelines and Examples
5.10.1. SPI Controller Differences Among Intel SoC Device Families
5.10.2. SPI Controller Use Cases
5.10.3. SPI Controller Features
5.10.4. SPI Controller System Integration
5.10.5. SPI Controller Signal Description
5.10.6. SPI Controller Functional Description
5.10.7. SPI Controller Programming Model
5.10.8. SPI Controller Address Map and Register Definitions
5.10.6.1. Protocol Details and Standards Compliance
5.10.6.2. Overview
5.10.6.3. Serial Bit-Rate Clocks
5.10.6.4. Transmit and Receive FIFO Buffers
5.10.6.5. SPI Interrupts
5.10.6.6. Transfer Modes
5.10.6.7. SPI Master
5.10.6.8. SPI Slave
5.10.6.9. Partner Connection Interfaces
5.10.6.10. DMA Controller Interface
5.10.6.11. Slave Interface
5.10.6.12. Clocks and Resets
5.12.1. Watchdog Timers Differences Among Intel SoC Device Families
5.12.2. Watchdog Timers Use Cases
5.12.3. Watchdog Timers Features
5.12.4. Watchdog Timers System Integration
5.12.5. Watchdog Timers Functional Description
5.12.6. Watchdog Timers Programming Model
5.12.7. Watchdog Timers Address Map and Register Definitions
5.12.6.1. Setting the Timeout Period Values
5.12.6.2. Selecting the Output Response Mode
5.12.6.3. Enabling and Initially Starting a Watchdog Timers
5.12.6.4. Reloading a Watchdog Counter
5.12.6.5. Pausing a Watchdog Timers
5.12.6.6. Disabling and Stopping a Watchdog Timers
5.12.6.7. Watchdog Timers State Machine
5.13.1. UART Controller Differences Among Intel SoC Device Families
5.13.2. UART Controller Use Cases
5.13.3. UART Controller Features
5.13.4. UART Controller System Integration
5.13.5. UART Controller Signal Description
5.13.6. UART Controller Functional Description
5.13.7. UART Controller Address Map and Register Definitions
5.13.8. UART Controller Design Guidelines and Example