Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
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7.6.11. CoreSight Clocks
The ARM CoreSight Debug logic consists of both the CoreSight components in the MPU sub-system and the CoreSight DAP and Trace components themselves. The diagram below shows the details.
The following tables show clock information for the CoreSight clocks based on clock source.
Clock Name | HPS Clock Source | Clock Destination | Description |
---|---|---|---|
tpiu_trace_clk_hio,tpiu_trace_clk_div2 | TPIU | FPGA LE -> Pin | Trace clock generated by TPIU, ½ of tpiu_trace_clkin. Also duplicated output on FPGA interface left. |
Clock | Source | Destination | Description |
---|---|---|---|
hps_jtag_tck | Input pin | HPS JTAG TAP controller | External HPS JTAG Clock input |
tpiu_trace_clkin | Input pin or from FPGA fabric | CoreSight TPIU | Alternate clock source from FPGA fabric to clock all TPIU Trace Port transactions out of the HPS |
The following table shows the registers used to program the clocks.
Clock Name | *.src | *.cnt (n+1 divider) | *.div (2^n divider) | Clock Gate (enable) |
---|---|---|---|---|
cs_at_clk | mainpllgrp.nocclk.src = 0 (Main_PLL_C3) = 1 (Peri_PLL_C1) |
--- | mainpllgrp.nocdiv.csclk | mainpllgrp.en.csclken |
cs_pdbg_clk | mainpllgrp.nocdiv.cspdbgclk | |||
cs_trace_clk | mainpllgrp.nocdiv.cstraceclk |