Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

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Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History 2. Introduction to the Hard Processor System 3. Micro Processor Unit (MPU) 4. Application Processor Subsystem 5. Peripheral Subsystem 6. System Manager 7. Clock Manager 8. Reset Manager 9. Power Management 10. Address Map 11. Bridges 12. Interfaces 13. System Interconnect and Firewalls 14. Error Checking and Correction Controller 15. CoreSight Debug and Trace 16. HPS Register Map A. Appendix
1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History x
1.1. Introduction to the HPS Revision History 1.2. MPU Revision History 1.3. CCU Revision History 1.4. GIC Revision History 1.5. SMMU Revision History 1.6. On-Chip RAM Revision History 1.7. EMAC Revision History 1.8. DMA Controller Revision History 1.9. NAND Flash Controller Revision History 1.10. SD/eMMC Revision History 1.11. Combo DLL PHY Revision History 1.12. USB 3.1 Gen1 Controller Revision History 1.13. USB 2.0 OTG Controller Revision History 1.14. I3C Controller Revision History 1.15. I2C Controller Revision History 1.16. SPI Controller Revision History 1.17. Timers Revision History 1.18. Watchdog Timers Revision History 1.19. UART Controller Revision History 1.20. GPIO Revision History 1.21. I/O Pin Multiplexing Revision History 1.22. System Manager Revision History 1.23. Clock Manager Revision History 1.24. Reset Manager Revision History 1.25. Power Management Revision History 1.26. Bridges Revision History 1.27. HPS Mailbox Revision History 1.28. MPFE and MPFE-lite Revision History 1.29. EMAC GMII through FPGA Fabric Revision History 1.30. System Interconnect and Firewalls Revision History 1.31. ECC Controller Revision History 1.32. CoreSight* Debug and Trace Revision History 1.33. HPS Register Map Revision History 1.34. Booting and Configuration Revision History 1.35. HPS Use of SDM QSPI Controller Revision History 1.36. Security Revision History
2. Introduction to the Hard Processor System x
2.1. HPS Differences Among Intel SoC Device Families 2.2. HPS Features 2.3. HPS System Integration 2.4. HPS IP Revisions 2.5. HPS Address Map and Register Definitions
2.3. HPS System Integration x
2.3.1. HPS Block Diagram 2.3.2. MPU Features 2.3.3. Application Processor Subsystem 2.3.4. Peripheral Subsystem 2.3.5. System Manager Features 2.3.6. Clock Manager Features 2.3.7. Reset Manager Features 2.3.8. Bridges Features 2.3.9. System Interconnect and Firewalls Features 2.3.10. ECC Controller Features 2.3.11. CoreSight Debug and Trace Features
2.3.2. MPU Features x
2.3.2.1. Arm Cortex-A76 Core Features 2.3.2.2. Arm* Cortex* -A55 Core Features 2.3.2.3. Arm* DynamIQ Shared Unit Features
2.3.3. Application Processor Subsystem x
2.3.3.1. CCU Features 2.3.3.2. GIC Features 2.3.3.3. SMMU Features 2.3.3.4. On-Chip RAM Features
2.3.4. Peripheral Subsystem x
2.3.4.1. EMAC Features 2.3.4.2. DMA Controller Features 2.3.4.3. NAND Flash Controller Features 2.3.4.4. Combo DLL PHY Features 2.3.4.5. USB 3.1 Gen1 Controller Features 2.3.4.6. USB 2.0 OTG Controller Features 2.3.4.7. I3C Controller Features 2.3.4.8. I2C Controller Features 2.3.4.9. SPI Controller Features 2.3.4.10. Timers Features 2.3.4.11. Watchdog Timers Features 2.3.4.12. UART Controller Features 2.3.4.13. GPIO Features 2.3.4.14. I/O Pin Multiplexing Features
2.3.4.1. EMAC Features x
2.3.4.1.1. XGMAC Core 2.3.4.1.2. Time Sensitive Networking 2.3.4.1.3. MAC Transaction Layer 2.3.4.1.4. DMA 2.3.4.1.5. Management Interface 2.3.4.1.6. Synchronized Multidrop Timestamp Gathering Hub 2.3.4.1.7. External Memory 2.3.4.1.8. PHY Interface
3. Micro Processor Unit (MPU) x
3.1. MPU Differences Among Intel SoC Device Families 3.2. MPU Use Cases 3.3. MPU Features 3.4. MPU System Integration 3.5. MPU Arm* Cortex* -A76 Core 3.6. MPU Arm* Cortex* -A55 Core 3.7. MPU Arm* DynamIQ Shared Unit 3.8. MPU Clock Domains 3.9. MPU Reset Domains 3.10. MPU Power Domains 3.11. MPU Address Map and Register Definitions
3.5. MPU Arm* Cortex* -A76 Core x
3.5.1. Arm Cortex-A76 Core Features 3.5.2. System Integration of the Arm* Cortex* -A76 Core 3.5.3. Functional Description of the Arm Cortex-A76 Core
3.5.3. Functional Description of the Arm Cortex-A76 Core x
3.5.3.1. Cortex* -A76 Core Configuration 3.5.3.2. Exception Levels 3.5.3.3. Virtualization 3.5.3.4. Memory Management Unit 3.5.3.5. Level 1 Memory System 3.5.3.6. Level 2 Memory System 3.5.3.7. Generic Interrupt Controller CPU Interface 3.5.3.8. Advanced Single Instruction Multiple Data and Floating Point Support 3.5.3.9. Cryptographic Extensions 3.5.3.10. Generic Timer 3.5.3.11. Cache Protection 3.5.3.12. Debug
3.5.3.2. Exception Levels x
3.5.3.2.1. Security State 3.5.3.2.2. Security Model
3.5.3.4. Memory Management Unit x
3.5.3.4.1. Translation Lookaside Buffer 3.5.3.4.2. Translation Match Process 3.5.3.4.3. Translation Table Walks
3.5.3.5. Level 1 Memory System x
3.5.3.5.1. Instruction Cache 3.5.3.5.2. Data Cache 3.5.3.5.3. Data Prefetching
3.5.3.11. Cache Protection x
3.5.3.11.1. Uncorrected Errors and Data Poisoning 3.5.3.11.2. Reliability, Availability, and Serviceability Error Types 3.5.3.11.3. Error Recording 3.5.3.11.4. Error Injection
3.5.3.12. Debug x
3.5.3.12.1. Breakpoints and Watchpoints 3.5.3.12.2. Performance Monitoring Unit 3.5.3.12.3. Activity Monitor Unit 3.5.3.12.4. Embedded Trace Macrocell
3.6. MPU Arm* Cortex* -A55 Core x
3.6.1. Arm* Cortex* -A55 Core Features 3.6.2. System Integration of the Arm* Cortex* -A55 Core 3.6.3. Functional Description of the Arm* Cortex* -A55 Core
3.6.3. Functional Description of the Arm* Cortex* -A55 Core x
3.6.3.1. Cortex* -A55 Core Configuration 3.6.3.2. Exception Levels 3.6.3.3. Virtualization 3.6.3.4. Memory Management Unit 3.6.3.5. Level 1 Memory System 3.6.3.6. Level 2 Memory System 3.6.3.7. Generic Interrupt Controller CPU Interface 3.6.3.8. Data Processing Unit 3.6.3.9. Generic Timer 3.6.3.10. Cache Protection 3.6.3.11. Debug
3.6.3.2. Exception Levels x
3.6.3.2.1. Security State 3.6.3.2.2. Security Model
3.6.3.4. Memory Management Unit x
3.6.3.4.1. Translation Lookaside Buffer 3.6.3.4.2. Translation Match Process 3.6.3.4.3. Translation Table Walks
3.6.3.10. Cache Protection x
3.6.3.10.1. Uncorrected Errors and Data Poisoning 3.6.3.10.2. Reliability, Availability and Serviceability Error Types 3.6.3.10.3. Error Reporting 3.6.3.10.4. Error Injection
3.6.3.11. Debug x
3.6.3.11.1. Breakpoints and Watchpoints 3.6.3.11.2. Performance Monitoring Unit 3.6.3.11.3. Embedded Trace Macrocell
3.7. MPU Arm* DynamIQ Shared Unit x
3.7.1. Arm* DynamIQ Shared Unit Features 3.7.2. System Integration of the Arm* DynamIQ Shared Unit 3.7.3. Functional Description of the Arm* DynamIQ Shared Unit
3.7.3. Functional Description of the Arm* DynamIQ Shared Unit x
3.7.3.1. DSU Configuration 3.7.3.2. Level 3 Cache 3.7.3.3. Interfaces 3.7.3.4. Debug
3.7.3.2. Level 3 Cache x
3.7.3.2.1. Cache Allocation Policy 3.7.3.2.2. Cache Partitioning 3.7.3.2.3. Cache Data RAM Latency 3.7.3.2.4. Cache Slices and Portions
3.7.3.4. Debug x
3.7.3.4.1. DebugBlock 3.7.3.4.2. Embedded Cross Trigger 3.7.3.4.3. Performance Monitoring Unit
4. Application Processor Subsystem x
4.1. Cache Coherency Unit (CCU) 4.2. Generic Interrupt Controller (GIC) 4.3. System Memory Management Unit (SMMU) 4.4. On-Chip RAM
4.1. Cache Coherency Unit (CCU) x
4.1.1. CCU Differences Among Intel SoC Device Families 4.1.2. CCU Use Cases 4.1.3. CCU Features 4.1.4. CCU System Integration 4.1.5. CCU Functional Description 4.1.6. CCU Programming Model 4.1.7. CCU Address Map and Register Definitions
4.1.5. CCU Functional Description x
4.1.5.1. Block Diagram 4.1.5.2. Ports 4.1.5.3. Cache Coherency Protocol 4.1.5.4. Addressing and Memory Regions 4.1.5.5. Connectivity 4.1.5.6. Snoop Filters 4.1.5.7. System Memory Cache 4.1.5.8. Credits and Resources 4.1.5.9. Quality of Service 4.1.5.10. Storage Protection 4.1.5.11. Exclusive Monitors 4.1.5.12. Firewall and Security 4.1.5.13. Interrupts 4.1.5.14. Clocks 4.1.5.15. Resets 4.1.5.16. Power Management 4.1.5.17. Shutdown of Interfaces 4.1.5.18. Error Handling 4.1.5.19. CCU Restrictions
4.1.5.1. Block Diagram x
4.1.5.1.1. Coherent Agent Interface Unit (CAIU) 4.1.5.1.2. Non-coherent Agent Interface Unit (NCAIU) 4.1.5.1.3. Distributed Coherence Engine (DCE) 4.1.5.1.4. Distributed Memory Interface (DMI) 4.1.5.1.5. Distributed Virtual Memory Engine (DVE) 4.1.5.1.6. Distributed I/O Interface (DII)
4.1.5.2. Ports x
4.1.5.2.1. DSU CHI-B Initiator Port 4.1.5.2.2. F2H ACE-Lite Initiator Port 4.1.5.2.3. GIC_M ACE-lite Initiator Port 4.1.5.2.4. TCU Ace-lite+DVM Initiator Port 4.1.5.2.5. CCU_IOM ACE-Lite Initiator Port 4.1.5.2.6. CCU_DMI0, CCU_DMI1 1AXI4 Target Ports 4.1.5.2.7. CCU_IOS AXI Target Port 4.1.5.2.8. MPFE CSR AXI Target Port 4.1.5.2.9. GIC AXI Target Port 4.1.5.2.10. OCRAM AXI Target Port
4.1.5.3. Cache Coherency Protocol x
4.1.5.3.1. Coherent Read Request 4.1.5.3.2. Coherent Clean Request 4.1.5.3.3. Coherent Write Request
4.1.5.4. Addressing and Memory Regions x
4.1.5.4.1. Ncore Register Space 4.1.5.4.2. General Purpose Address Space 4.1.5.4.3. Boot Address Space 4.1.5.4.4. Interleaving
4.1.5.4.2. General Purpose Address Space x
4.1.5.4.2.1. Address Map When Using a Single SDRAM Channel 4.1.5.4.2.2. Address Map When Using Multiple SDRAM Channels
4.1.5.12. Firewall and Security x
4.1.5.12.1. OCRAM Firewall 4.1.5.12.2. GIC Firewall 4.1.5.12.3. Service Network Access 4.1.5.12.4. AXI APROT Tunneling
4.1.5.15. Resets x
4.1.5.15.1. Q-Channel
4.1.5.18. Error Handling x
4.1.5.18.1. Correctable Errors 4.1.5.18.2. Uncorrectable Errors
4.1.5.19. CCU Restrictions x
4.1.5.19.1. CHI Support 4.1.5.19.2. AXI and ACE Support 4.1.5.19.3. Ordering Support
4.1.6. CCU Programming Model x
4.1.6.1. CCU Initialization 4.1.6.2. Boot Region CSR Default Settings 4.1.6.3. Error Registers
4.1.6.1. CCU Initialization x
4.1.6.1.1. Address Space Configuration 4.1.6.1.2. SMC Configuration
4.2. Generic Interrupt Controller (GIC) x
4.2.1. GIC Differences Among Intel® SoC Device Families 4.2.2. GIC Features 4.2.3. GIC System Integration 4.2.4. GIC Functional Description 4.2.5. GIC Programming Model 4.2.6. GIC Address Map and Register Definitions
4.2.4. GIC Functional Description x
4.2.4.1. Types of Interrupts 4.2.4.2. Clock Domains 4.2.4.3. Reset Domains
4.2.5. GIC Programming Model x
4.2.5.1. GIC Shared Peripheral Interrupts Map for the SoC HPS
4.3. System Memory Management Unit (SMMU) x
4.3.1. SMMU Differences Among Intel SoC Device Families 4.3.2. SMMU Use Cases 4.3.3. SMMU Features 4.3.4. SMMU System Integration 4.3.5. SMMU Signal Description 4.3.6. SMMU Functional Description 4.3.7. SMMU Programming Model 4.3.8. SMMU Address Map and Register Definitions 4.3.9. SMMU Design Guidelines and Examples
4.3.3. SMMU Features x
4.3.3.1. DTI Interface for TCU 4.3.3.2. Stage2 Translation 4.3.3.3. TLB 4.3.3.4. Bypass Mode 4.3.3.5. APB4 Programming Interface
4.3.4. SMMU System Integration x
4.3.4.1. TBU Instances 4.3.4.2. DTI Interconnect Topology 4.3.4.3. MMU-600 interfaces 4.3.4.4. IP Configuration
4.3.4.3. MMU-600 interfaces x
4.3.4.3.1. TCU Interfaces 4.3.4.3.2. TBU Interfaces 4.3.4.3.3. DTI Interconnect Interfaces
4.3.4.3.1. TCU Interfaces x
4.3.4.3.1.1. APB4 Programming Interface 4.3.4.3.1.2. ACE-Lite Manager for Table walk and DVM for TCU 4.3.4.3.1.3. LPI Interfaces for TCU 4.3.4.3.1.4. DTI Interface for TCU 4.3.4.3.1.5. SYSCO Interface for TCU 4.3.4.3.1.6. PMU snapshot Interface for TCU
4.3.4.3.2. TBU Interfaces x
4.3.4.3.2.1. ACE-Lite Subordinate Interface 4.3.4.3.2.2. ACE-Lite Manager Interface 4.3.4.3.2.3. DTI interface for TBU 4.3.4.3.2.4. LPI Interfaces for TBU 4.3.4.3.2.5. Interrupt Interfaces for TBU
4.3.4.3.3. DTI Interconnect Interfaces x
4.3.4.3.3.1. DTI Interconnect Switch Interfaces 4.3.4.3.3.2. DTI Interconnect Sizer Interfaces 4.3.4.3.3.3. DTI Interconnect Register Slice Interfaces
4.3.4.4. IP Configuration x
4.3.4.4.1. MMU-600 TCU Hardware Configuration 4.3.4.4.2. MMU-600 TBU Hardware Configurations 4.3.4.4.3. MMU-600 DTI Switch Hardware Configuration 4.3.4.4.4. MMU-600 DTI Async Bridge configuration
4.3.5. SMMU Signal Description x
4.3.5.1. MMU-600 TCU Configuration Signals 4.3.5.2. MMU-600 TBU Configuration Signals 4.3.5.3. TBU with Untranslated Interface
4.3.6. SMMU Functional Description x
4.3.6.1. Block Diagram 4.3.6.2. Functional Blocks 4.3.6.3. Functional Modes 4.3.6.4. Interrupts
4.3.6.3. Functional Modes x
4.3.6.3.1. Address Translation 4.3.6.3.2. Stage1 Translation 4.3.6.3.3. Stage2 Translation 4.3.6.3.4. TLB 4.3.6.3.5. Bypass Mode
4.3.6.4. Interrupts x
4.3.6.4.1. Interrupt Interfaces for TBU
4.3.7. SMMU Programming Model x
4.3.7.1. Initializing the SMMU 4.3.7.2. Assigning Stream IDs 4.3.7.3. Allocating the Command Queue 4.3.7.4. Allocating the Event Queue 4.3.7.5. Configuring the Stream Table 4.3.7.6. Initializing the Command Queue 4.3.7.7. Initializing the Event Queue 4.3.7.8. Invalidate TLBs and Configuration caches 4.3.7.9. Create Context Descriptor 4.3.7.10. Creating Stream Table Entry 4.3.7.11. Enabling the SMMU
4.3.8. SMMU Address Map and Register Definitions x
4.3.8.1. TBU Private Registers
4.3.8.1. TBU Private Registers x
4.3.8.1.1. TBU Stream Control Register[m][n] 4.3.8.1.2. TBU Stream ID Ax Register[m][n]
4.3.9. SMMU Design Guidelines and Examples x
4.3.9.1. F2SDRAM_TBU Special Handling 4.3.9.2. Translation Table Walk Sequence
4.3.9.2. Translation Table Walk Sequence x
4.3.9.2.1. Calculating Page Table Walks
4.4. On-Chip RAM x
4.4.1. On-Chip RAM Differences Among Intel SoC Device Families 4.4.2. On-Chip RAM Use Cases 4.4.3. On-Chip RAM Features 4.4.4. On-Chip RAM Functional Description 4.4.5. On-Chip RAM Address Map and Register Definitions
4.4.4. On-Chip RAM Functional Description x
4.4.4.1. Read and Write Double-Bit Bus Errors 4.4.4.2. On-Chip RAM Controller 4.4.4.3. On-Chip RAM Burst Support 4.4.4.4. Exclusive Access Support 4.4.4.5. Sub-word Accesses 4.4.4.6. On-Chip RAM Clocks 4.4.4.7. On-Chip RAM Resets 4.4.4.8. On-Chip RAM Initialization 4.4.4.9. ECC Protection
4.4.4.5. Sub-word Accesses x
4.4.4.5.1. Pipeline and Timing
5. Peripheral Subsystem x
5.1. Ethernet Media Access Controller 5.2. DMA Controller 5.3. NAND Flash Controller 5.4. SD/eMMC Host Controller 5.5. Combo DLL PHY 5.6. USB 3.1 Gen1 Controller 5.7. USB 2.0 OTG Controller 5.8. I3C Controller 5.9. I2C Controller 5.10. SPI Controller 5.11. Timers 5.12. Watchdog Timers 5.13. UART Controller 5.14. General-Purpose I/O Interface (GPIO) 5.15. Hard Processor System I/O Pin Multiplexing
5.1. Ethernet Media Access Controller x
5.1.1. EMAC Differences Among Intel SoC Device Families 5.1.2. EMAC Use Cases 5.1.3. EMAC Features 5.1.4. EMAC System Integration 5.1.5. EMAC Signal Description and Interfaces 5.1.6. EMAC Functional Description 5.1.7. EMAC Programming Model 5.1.8. EMAC Address Map and Register Definitions 5.1.9. EMAC Design Guidelines and Examples
5.1.3. EMAC Features x
5.1.3.1. XGMAC Core 5.1.3.2. Time Sensitive Networking 5.1.3.3. MAC Transaction Layer 5.1.3.4. DMA 5.1.3.5. Management Interface 5.1.3.6. Synchronized Multidrop Timestamp Gathering Hub 5.1.3.7. External Memory 5.1.3.8. PHY Interface
5.1.4. EMAC System Integration x
5.1.4.1. EMAC Block Diagram and Overview 5.1.4.2. EMAC System Integration
5.1.5. EMAC Signal Description and Interfaces x
5.1.5.1. HPS EMAC I/O Signals 5.1.5.2. FPGA EMAC I/O Signals 5.1.5.3. PHY Management Interface 5.1.5.4. SMTG Hub Signals and Interface 5.1.5.5. Timestamp Interface Signals 5.1.5.6. DMA Host Interface 5.1.5.7. System Manager Configuration Interface
5.1.5.3. PHY Management Interface x
5.1.5.3.1. MDIO Interface 5.1.5.3.2. I2C External PHY Management Interface
5.1.6. EMAC Functional Description x
5.1.6.1. External Memory 5.1.6.2. DMA Controller 5.1.6.3. Descriptor 5.1.6.4. Checksum Offload Engine (COE) 5.1.6.5. TCP Segmentation Offload 5.1.6.6. Packet Filtering 5.1.6.7. Management Counter 5.1.6.8. Flow Control 5.1.6.9. IEEE 1588-2008 Advanced Timestamp 5.1.6.10. TSN Features 5.1.6.11. SMTG Hub Time of Day Synchronization 5.1.6.12. Clocks 5.1.6.13. Resets 5.1.6.14. Interrupts
5.1.6.1. External Memory x
5.1.6.1.1. Transmit and Receive Data FIFO Buffers 5.1.6.1.2. TCP/IP Segmentation Offload Memory 5.1.6.1.3. Descriptor Cache Memory 5.1.6.1.4. Gate Control List Memory
5.1.6.2. DMA Controller x
5.1.6.2.1. Application Bus Burst Access 5.1.6.2.2. Application Data Buffer Alignment 5.1.6.2.3. Buffer Size Calculations 5.1.6.2.4. DMA Descriptor Fetch Operation 5.1.6.2.5. DMA TX Data Transfer Operation 5.1.6.2.6. DMA RX Data Transfer Operation 5.1.6.2.7. DMA Descriptor Write-Back Operation 5.1.6.2.8. DMA Start/Stop Operation 5.1.6.2.9. Memory Cache Size Requirements 5.1.6.2.10. Memory Cache Access Arbitration 5.1.6.2.11. DMA Error Handling
5.1.6.2.11. DMA Error Handling x
5.1.6.2.11.1. TX DMA Bus Error Handling Flow 5.1.6.2.11.2. RX DMA Bus Error Handling Flow
5.1.6.3. Descriptor x
5.1.6.3.1. Descriptor Structure 5.1.6.3.2. Descriptor Endianness 5.1.6.3.3. Transmit Descriptor 5.1.6.3.4. Receive Descriptor 5.1.6.3.5. Enhanced Descriptor for Time-Based Scheduling 5.1.6.3.6. Header Payload Split Support
5.1.6.5. TCP Segmentation Offload x
5.1.6.5.1. Description of the TSO Feature 5.1.6.5.2. DMA Operation with TSO Feature 5.1.6.5.3. TCP/IP Header Fields 5.1.6.5.4. Header and Payload Fields of Segmented Packets 5.1.6.5.5. Context Descriptor Sequence
5.1.6.6. Packet Filtering x
5.1.6.6.1. Source Address or Destination Address Filtering 5.1.6.6.2. VLAN Filtering 5.1.6.6.3. Extended VLAN Filtering 5.1.6.6.4. Layer 3 and Layer 4 Match Filtering
5.1.6.8. Flow Control x
5.1.6.8.1. Transmit Flow Control 5.1.6.8.2. Receive Flow Control
5.1.6.9. IEEE 1588-2008 Advanced Timestamp x
5.1.6.9.1. Delay Request-Response Mechanism 5.1.6.9.2. Peer-to-Peer PTP Transparent Clock Message Support 5.1.6.9.3. Clock Types 5.1.6.9.4. Reference Timing Source 5.1.6.9.5. System Time Register Module 5.1.6.9.6. Transmit Path Functions 5.1.6.9.7. Receive Path Functions
5.1.6.10. TSN Features x
5.1.6.10.1. Enhancements to Scheduled Traffic 5.1.6.10.2. Frame Preemption 5.1.6.10.3. Time-Based Scheduling 5.1.6.10.4. Credit Based Shaper
5.1.6.11. SMTG Hub Time of Day Synchronization x
5.1.6.11.1. SMTG Hub Overview 5.1.6.11.2. SMTG Hub Logic 5.1.6.11.3. SMTG Hub Integration with the HPS and FPGA
5.1.6.12. Clocks x
5.1.6.12.1. Clock Domain
5.1.6.13. Resets x
5.1.6.13.1. EMAC ECC RAM Reset 5.1.6.13.2. EMAC Software Reset
5.1.7. EMAC Programming Model x
5.1.7.1. System Level EMAC configurable Registers 5.1.7.2. EMAC HPS Interface Initialization 5.1.7.3. EMAC FPGA Interface Initialization 5.1.7.4. DMA Initialization 5.1.7.5. EMAC Initialization and Configuration 5.1.7.6. Performing Normal Receive and Transmit Operation 5.1.7.7. Stopping and Starting Transmission 5.1.7.8. Reconfiguring the DMA Registers 5.1.7.9. Switching to a New Descriptor List in the Receive DMA 5.1.7.10. Handling Bus Errors and Recovery 5.1.7.11. Setting up TCP Segmentation Offload 5.1.7.12. Setting up VLAN Filtering on Receive 5.1.7.13. Setting up Extended VLAN Filtering 5.1.7.14. Setting up the L3-L4 Filtering 5.1.7.15. Programming the SMTG Hub 5.1.7.16. Setting up the IEEE 1588 PTP Timestamping 5.1.7.17. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output 5.1.7.18. Programming the GCL and GCL Linked Registers 5.1.7.19. Programming Guidelines for EST 5.1.7.20. Enabling the Frame Preemption Function 5.1.7.21. Setting up the Time-Based Scheduling Function
5.1.7.1. System Level EMAC configurable Registers x
5.1.7.1.1. System Manager Configurable Registers 5.1.7.1.2. Clock Manager Configurable Registers 5.1.7.1.3. Reset Manager Configurable Registers
5.1.7.10. Handling Bus Errors and Recovery x
5.1.7.10.1. Transmit DMA Channel 5.1.7.10.2. Receive DMA Channel
5.1.7.14. Setting up the L3-L4 Filtering x
5.1.7.14.1. Writing to the Indirect Addressed Registers 5.1.7.14.2. Reading the Indirect Addressed Registers
5.1.7.16. Setting up the IEEE 1588 PTP Timestamping x
5.1.7.16.1. Initialization Guidelines for System Time Generation 5.1.7.16.2. Coarse Correction Method 5.1.7.16.3. Fine-Correction Method
5.1.7.17. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output x
5.1.7.17.1. Generating a Single Pulse on PPS 5.1.7.17.2. Generating a Pulse Train on PPS 5.1.7.17.3. Generating an Interrupt without Affecting the PPS
5.1.7.20. Enabling the Frame Preemption Function x
5.1.7.20.1. Receive Side Programming 5.1.7.20.2. Transmit Side Programming
5.1.9. EMAC Design Guidelines and Examples x
5.1.9.1. HPS RGMII System Integration 5.1.9.2. Interface to HPS IO Pins 5.1.9.3. RGMII Clock Skew Guidelines
5.1.9.3. RGMII Clock Skew Guidelines x
5.1.9.3.1. Use Case 1 – Utilize Programmable HPS I/O Delay Feature 5.1.9.3.2. Use Case 2 – Configure External PHY RGMII-Internal Delay (RGMII-ID) 5.1.9.3.3. Use Case 3 – Introduce Board Trace Delay
5.2. DMA Controller x
5.2.1. DMA Controller Differences Among Intel SoC Device Families 5.2.2. DMA Controller Use Cases 5.2.3. DMA Controller Features 5.2.4. DMA Controller System Integration 5.2.5. DMA Controller Functional Description 5.2.6. DMA Controller Address Map and Register Definitions
5.2.5. DMA Controller Functional Description x
5.2.5.1. Flow Control 5.2.5.2. Handshaking Interface 5.2.5.3. Interrupt Outputs 5.2.5.4. DMA Controller Peripheral Request Interface
5.2.5.4. DMA Controller Peripheral Request Interface x
5.2.5.4.1. Peripheral Request Interface Mapping
5.3. NAND Flash Controller x
5.3.1. NAND Flash Controller Differences Among Intel SoC Device Families 5.3.2. NAND Flash Controller Use Cases 5.3.3. NAND Flash Controller Features 5.3.4. NAND Flash Controller System Integration 5.3.5. NAND Flash Controller Signal Description 5.3.6. NAND Flash Controller Functional Description 5.3.7. NAND Flash Controller Programming Model 5.3.8. NAND Flash Controller Address Map and Register Definitions
5.3.5. NAND Flash Controller Signal Description x
5.3.5.1. Device Discovery Interface 5.3.5.2. Write Protection Interface 5.3.5.3. Interrupt Interface 5.3.5.4. DFI Interface
5.3.6. NAND Flash Controller Functional Description x
5.3.6.1. Block Diagram 5.3.6.2. Initialization Protocol (Device Discovery) 5.3.6.3. NAND Flash Addressing and Data Layout 5.3.6.4. Command Engine Functionality 5.3.6.5. ECC Engine Functionality 5.3.6.6. Control Data Mechanism 5.3.6.7. Remapping Mechanism 5.3.6.8. Write Protection Mechanism 5.3.6.9. Error and Special Scenarios Handling 5.3.6.10. Controller Fixed Parameters and Clock Frequencies Supported
5.3.6.3. NAND Flash Addressing and Data Layout x
5.3.6.3.1. NAND Flash Addressing 5.3.6.3.2. Data Layout 5.3.6.3.3. Layout Between Pages
5.3.6.4. Command Engine Functionality x
5.3.6.4.1. Command Engine Architecture 5.3.6.4.2. CDMA Work Mode 5.3.6.4.3. PIO Work Mode 5.3.6.4.4. Generic Work Mode 5.3.6.4.5. Extended Functionality in Command Engine
5.3.6.4.2. CDMA Work Mode x
5.3.6.4.2.1. Operation in CDMA Mode 5.3.6.4.2.2. Thread Synchronization Mechanism 5.3.6.4.2.3. NOP Descriptor
5.3.6.4.3. PIO Work Mode x
5.3.6.4.3.1. Operation in PIO Work Mode 5.3.6.4.3.2. Last Operation Status
5.3.6.4.4. Generic Work Mode x
5.3.6.4.4.1. Operation in Generic Work Mode 5.3.6.4.4.2. Last Operation Status 5.3.6.4.4.3. Switching To/From Generic Work Mode
5.3.6.4.5. Extended Functionality in Command Engine x
5.3.6.4.5.1. LUN Interleaving 5.3.6.4.5.2. Multipage Commands 5.3.6.4.5.3. Cache Commands 5.3.6.4.5.4. Multi-plane Commands 5.3.6.4.5.5. Thread Reset Commands 5.3.6.4.5.6. Timeout Functionality 5.3.6.4.5.7. Support of TLC (pSLC Mode) Devices
5.3.6.5. ECC Engine Functionality x
5.3.6.5.1. Error Correction 5.3.6.5.2. Sector Sizes 5.3.6.5.3. Bad Block Marker 5.3.6.5.4. Scrambling Support 5.3.6.5.5. Erased Page Detection Support
5.3.6.9. Error and Special Scenarios Handling x
5.3.6.9.1. Access to Protected Areas 5.3.6.9.2. Bus Error 5.3.6.9.3. NAND Device Error 5.3.6.9.4. Data Integrity Errors 5.3.6.9.5. ECC Errors 5.3.6.9.6. Descriptor/Command Error 5.3.6.9.7. DQS Error 5.3.6.9.8. Error Interrupt Generation 5.3.6.9.9. Recommended Error Handling Checking Software Flow
5.3.7. NAND Flash Controller Programming Model x
5.3.7.1. NAND Controller Registers Programming Model 5.3.7.2. Status Polling Configuration 5.3.7.3. Device Layout Configuration 5.3.7.4. Configure Multiplane and Cache Operations 5.3.7.5. ECC Enabling 5.3.7.6. Interrupts Configuration 5.3.7.7. Configuring Timing Registers 5.3.7.8. Switch from SDR to DDR Operation Mode 5.3.7.9. Switch from DDR to SDR Operation Mode 5.3.7.10. Slave DMA Programming 5.3.7.11. Data Pre-Fetching Mechanism 5.3.7.12. Data Integrity Mechanism 5.3.7.13. Enabling pSLC Mode for the TLC Devices
5.3.7.1. NAND Controller Registers Programming Model x
5.3.7.1.1. Programming SFR Registers 5.3.7.1.2. Programming Command Registers
5.4. SD/eMMC Host Controller x
5.4.1. SD/eMMC Differences Among Intel SoC Device Families 5.4.2. SD/eMMC Use Cases 5.4.3. SD/eMMC Features 5.4.4. SD/eMMC System Integration 5.4.5. SD/eMMC Signal Description 5.4.6. SD/eMMC Functional Description 5.4.7. SD/eMMC Programming Model 5.4.8. SD/eMMC Address Map and Register Definitions 5.4.9. SD/eMMC Design Guidelines and Examples
5.4.3. SD/eMMC Features x
5.4.3.1. Supported Standards 5.4.3.2. SD Support 5.4.3.3. eMMC Support 5.4.3.4. DMA Support
5.4.6. SD/eMMC Functional Description x
5.4.6.1. Block Diagram 5.4.6.2. Configuration 5.4.6.3. DMA Operation 5.4.6.4. Clocks 5.4.6.5. Resets 5.4.6.6. SD Voltage Switching 5.4.6.7. Timings on the SD/eMMC Interface 5.4.6.8. Command Queuing
5.4.6.1. Block Diagram x
5.4.6.1.1. Bus Interface Unit 5.4.6.1.2. Reset Control Module 5.4.6.1.3. Synchronization Module 5.4.6.1.4. Response Module 5.4.6.1.5. FIFO Interface Unit 5.4.6.1.6. Card Interface Unit 5.4.6.1.7. System Requester Interface 5.4.6.1.8. System Manager Interface 5.4.6.1.9. Host Settings Interface 5.4.6.1.10. Command Queue Settings
5.4.6.2. Configuration x
5.4.6.2.1. Host Capabilities
5.4.6.3. DMA Operation x
5.4.6.3.1. SDMA Operation 5.4.6.3.2. ADMA2 Operation 5.4.6.3.3. ADMA3 Operation 5.4.6.3.4. DMA Errors
5.4.6.5. Resets x
5.4.6.5.1. Controller Software Reset
5.4.6.7. Timings on the SD/eMMC Interface x
5.4.6.7.1. Tuning
5.4.6.7.1. Tuning x
5.4.6.7.1.1. Tuning Sequence for SD 5.4.6.7.1.2. Tuning Sequence for eMMC
5.4.6.8. Command Queuing x
5.4.6.8.1. Optional Modes of Operation 5.4.6.8.2. Task Execution Order
5.4.7. SD/eMMC Programming Model x
5.4.7.1. Combo PHY Register Interface 5.4.7.2. Pre-Initialization Sequence 5.4.7.3. Error Handling
5.4.7.1. Combo PHY Register Interface x
5.4.7.1.1. Read Access 5.4.7.1.2. Write Access
5.4.7.3. Error Handling x
5.4.7.3.1. Generic Operation Error Recovery 5.4.7.3.2. Command Queueing Error Recovery 5.4.7.3.3. Combo PHY Underrun/Overflow Error Recovery
5.4.9. SD/eMMC Design Guidelines and Examples x
5.4.9.1. SD Card Level Shifting
5.5. Combo DLL PHY x
5.5.1. Combo DLL PHY Differences Among Intel SoC Device Families 5.5.2. Combo DLL PHY Use Cases 5.5.3. Combo DLL PHY Features 5.5.4. Combo DLL PHY System Integration 5.5.5. Combo DLL PHY Signal Description 5.5.6. Combo DLL PHY Functional Description 5.5.7. Combo DLL PHY Programming Model 5.5.8. Combo DLL PHY Address Map and Register Definitions
5.5.6. Combo DLL PHY Functional Description x
5.5.6.1. Block Diagram 5.5.6.2. Operation Modes 5.5.6.3. Clocking 5.5.6.4. DLL Functionality 5.5.6.5. Write Data Path 5.5.6.6. Read Data Path 5.5.6.7. Generation of CE#, CLE, ALE, WP#, and RE# signals 5.5.6.8. Resets
5.5.6.4. DLL Functionality x
5.5.6.4.1. DLL Locking
5.5.6.5. Write Data Path x
5.5.6.5.1. DQS Write Signal Generation 5.5.6.5.2. Output Enable Signal Generation
5.5.6.6. Read Data Path x
5.5.6.6.1. Generation of Dynamic Termination Signal 5.5.6.6.2. Input Enable Signal Generation
5.5.7. Combo DLL PHY Programming Model x
5.5.7.1. Initialization Procedure 5.5.7.2. DLL Lock Debugging 5.5.7.3. DLL Secondary Delay Configuration 5.5.7.4. Handling FIFO DQS Overflow and Underrun 5.5.7.5. Tuning for SD/eMMC Interface
5.6. USB 3.1 Gen1 Controller x
5.6.1. USB 3.1 Gen1 Controller Differences Among Intel SoC Device Families 5.6.2. USB 3.1 Gen1 Controller Use Cases 5.6.3. USB 3.1 Gen1 Controller Features 5.6.4. USB 3.1 Gen1 Controller System Integration 5.6.5. USB 3.1 Gen1 Controller Functional Description 5.6.6. USB 3.1 Gen1 Controller Programming Model 5.6.7. USB 3.1 Gen1 Controller Address Map and Register Definitions 5.6.8. USB 3.1 Gen1 Controller Design Guidelines and Examples
5.6.3. USB 3.1 Gen1 Controller Features x
5.6.3.1. Unsupported Features
5.6.5. USB 3.1 Gen1 Controller Functional Description x
5.6.5.1. Manager Interface 5.6.5.2. AHB Subordinate Interface 5.6.5.3. Application interface Unit 5.6.5.4. Bus Management Unit 5.6.5.5. Packet FIFO Controller 5.6.5.6. RAM 5.6.5.7. MAC 5.6.5.8. DMA 5.6.5.9. Loopback 5.6.5.10. PHY Interfaces 5.6.5.11. USB 3.1 Gen1 Controller Clocks 5.6.5.12. USB 3.1 Gen1 Controller Resets
5.6.5.1. Manager Interface x
5.6.5.1.1. AXI Manager Interface
5.6.5.8. DMA x
5.6.5.8.1. Reception Flow Details 5.6.5.8.2. Transmission Flow Details
5.6.5.9. Loopback x
5.6.5.9.1. Software Loopback Mode 5.6.5.9.2. BIST Loopback Mode
5.6.5.10. PHY Interfaces x
5.6.5.10.1. USB 2.0 ULPI PHY 5.6.5.10.2. PIPE Interface 5.6.5.10.3. USB 3.1 Mode-switch Controller 5.6.5.10.4. USB Type-C Receptacle 5.6.5.10.5. Performance 5.6.5.10.6. Maximum USB Bandwidth
5.6.5.10.1. USB 2.0 ULPI PHY x
5.6.5.10.1.1. Signals
5.6.5.10.2. PIPE Interface x
5.6.5.10.2.1. IO Connection
5.6.5.10.3. USB 3.1 Mode-switch Controller x
5.6.5.10.3.1. USB3.1 Mode-switch Controller Signals
5.6.5.11. USB 3.1 Gen1 Controller Clocks x
5.6.5.11.1. Clock Enable 5.6.5.11.2. Clock Gating
5.6.5.12. USB 3.1 Gen1 Controller Resets x
5.6.5.12.1. Reset Requirements 5.6.5.12.2. Software Resets 5.6.5.12.3. Warm Reset
5.6.6. USB 3.1 Gen1 Controller Programming Model x
5.6.6.1. Programming Controller in Host Mode 5.6.6.2. Programming Controller in Device Mode
5.6.6.1. Programming Controller in Host Mode x
5.6.6.1.1. Initialization Phase 5.6.6.1.2. Host Controller Capability Registers 5.6.6.1.3. Programming Model 5.6.6.1.4. Device Initialization
5.6.6.2. Programming Controller in Device Mode x
5.6.6.2.1. Device Power-on or Soft Reset 5.6.6.2.2. Initialization on USB Reset 5.6.6.2.3. Initialization on Connect Done 5.6.6.2.4. Initialization on SetAddress Request 5.6.6.2.5. Initialization on SetConfiguration or SetInterface Request 5.6.6.2.6. Agilex 5 Programming Model 5.6.6.2.7. Controller as Host
5.6.8. USB 3.1 Gen1 Controller Design Guidelines and Examples x
5.6.8.1. USB 3.1 Gen1 Controller Wakeup and Power Control
5.7. USB 2.0 OTG Controller x
5.7.1. USB 2.0 OTG Controller Differences Among Intel SoC Device Families 5.7.2. USB 2.0 OTG Controller Use Cases 5.7.3. USB 2.0 OTG Controller Features 5.7.4. USB 2.0 OTG Controller System Integration 5.7.5. USB 2.0 OTG Controller Functional Description 5.7.6. USB 2.0 OTG Controller Programming Model 5.7.7. USB 2.0 OTG Controller Address Map and Register Definitions
5.7.4. USB 2.0 OTG Controller System Integration x
5.7.4.1. USB 2.0 ULPI PHY Signal Description
5.7.5. USB 2.0 OTG Controller Functional Description x
5.7.5.1. Distributed Virtual Memory Support 5.7.5.2. Initiator Interface 5.7.5.3. Target Interface 5.7.5.4. USB OTG Controller Components 5.7.5.5. DMA 5.7.5.6. Local Memory Buffer 5.7.5.7. Clocks 5.7.5.8. Resets 5.7.5.9. Interrupts
5.7.5.4. USB OTG Controller Components x
5.7.5.4.1. Application Interface Unit 5.7.5.4.2. Packet FIFO Controller 5.7.5.4.3. SPRAM 5.7.5.4.4. MAC 5.7.5.4.5. Wakeup and Power Control 5.7.5.4.6. PHY Interface Unit
5.7.5.4.4. MAC x
5.7.5.4.4.1. USB Transactions 5.7.5.4.4.2. Host Protocol 5.7.5.4.4.3. Device Protocol 5.7.5.4.4.4. OTG Protocol
5.7.5.7. Clocks x
5.7.5.7.1. Clock Gating
5.7.5.8. Resets x
5.7.5.8.1. Reset Requirements 5.7.5.8.2. Hardware Reset 5.7.5.8.3. Software Reset 5.7.5.8.4. Taking the USB 2.0 OTG Controller Out of Reset
5.7.6. USB 2.0 OTG Controller Programming Model x
5.7.6.1. Enabling SPRAM ECCs 5.7.6.2. Host Initialization 5.7.6.3. Host Transaction 5.7.6.4. Device Initialization 5.7.6.5. Device Transaction
5.7.6.5. Device Transaction x
5.7.6.5.1. IN Transactions 5.7.6.5.2. OUT Transactions 5.7.6.5.3. Control Transfers
5.8. I3C Controller x
5.8.1. I3C Controller Differences Among Intel SoC Device Families 5.8.2. I3C Controller Use Cases 5.8.3. I3C Controller Features 5.8.4. I3C Controller System Integration 5.8.5. I3C Controller Signal Description 5.8.6. I3C Controller Functional Description 5.8.7. I3C Controller Programming Model 5.8.8. I3C Controller Address Map and Register Definitions 5.8.9. I3C Controller Design Guidelines and Examples
5.8.5. I3C Controller Signal Description x
5.8.5.1. Interface to HPS I/O 5.8.5.2. FPGA Routing
5.8.6. I3C Controller Functional Description x
5.8.6.1. Device Address 5.8.6.2. In-Band Interrupt (IBI) 5.8.6.3. Simple-Transfer DMA (SDMA) Handshake 5.8.6.4. Interrupts in I3C Controller 5.8.6.5. Overview of Master Role in I3C 5.8.6.6. Overview of Slave Role in I3C
5.8.6.5. Overview of Master Role in I3C x
5.8.6.5.1. Dynamic Address Assignment (DAA) 5.8.6.5.2. In-Band Interrupt (IBI) Detection and Handling 5.8.6.5.3. I3C Slave Interrupt Request (SIR) 5.8.6.5.4. Disabling I3C Master 5.8.6.5.5. Aborting Transfers of I3C Master 5.8.6.5.6. I3C Master Request (MR) 5.8.6.5.7. Master Command Data Structures 5.8.6.5.8. Response Data Structure 5.8.6.5.9. Operation Modes of I3C Controller 5.8.6.5.10. SCL Generation and Timings Based on Bus Configuration 5.8.6.5.11. Derivation of I3C/I2C Timing Parameters from Timing Registers 5.8.6.5.12. Error Detection 5.8.6.5.13. Defining Byte Support 5.8.6.5.14. Broadcast CCCs in I2C Speed 5.8.6.5.15. BUS RESET Generation DMA Controller Interface
5.8.6.5.1. Dynamic Address Assignment (DAA) x
5.8.6.5.1.1. SETDASA (Format 1: Primary) 5.8.6.5.1.2. SETDASA (Format 2: Point-to-Point) 5.8.6.5.1.3. ENTDAA 5.8.6.5.1.4. SETAASA
5.8.6.5.3. I3C Slave Interrupt Request (SIR) x
5.8.6.5.3.1. SIR Response Control
5.8.6.5.6. I3C Master Request (MR) x
5.8.6.5.6.1. MR Response Control
5.8.6.5.7. Master Command Data Structures x
5.8.6.5.7.1. Transfer Command Data Structure 5.8.6.5.7.2. Transfer Argument Data Structure 5.8.6.5.7.3. Short Data Argument Data Structure 5.8.6.5.7.4. Address Assignment Command Data Structure
5.8.6.5.9. Operation Modes of I3C Controller x
5.8.6.5.9.1. Single Data Rate (SDR) Transfers in Master Mode 5.8.6.5.9.2. Broadcast CCC Write Transfers 5.8.6.5.9.3. Directed Write and Read Transfers 5.8.6.5.9.4. Directed CCC Transfer Targeted to Multiple Slaves 5.8.6.5.9.5. I3C Private Write or Read Transfers 5.8.6.5.9.6. I2C Private Write or Read Transfers 5.8.6.5.9.7. Implication of TX-FIFO Empty and RX-FIFO Full Conditions 5.8.6.5.9.8. Implication of TOC and ROC Bit Settings for SDR Transfers
5.8.6.5.12. Error Detection x
5.8.6.5.12.1. Detecting Error Type in the Processed Commands 5.8.6.5.12.2. SDR Error Detection and Recovery Methods
5.8.6.6. Overview of Slave Role in I3C x
5.8.6.6.1. Description of the Slave Role in I3C 5.8.6.6.2. I3C versus I2C Role Selection 5.8.6.6.3. Slave Role Related Registers 5.8.6.6.4. Handling Address Assignment 5.8.6.6.5. CCC Transfers with I3C Slave 5.8.6.6.6. Private Data Transfers 5.8.6.6.7. Handling Private Transmit (Master Read) Transfers 5.8.6.6.8. Slave Interrupt Request Generation 5.8.6.6.9. Master Request Generation 5.8.6.6.10. Disabling I3C Slave 5.8.6.6.11. Data Structure in I3C Slave
5.8.6.6.6. Private Data Transfers x
5.8.6.6.6.1. Overview of Private Data Transfers
5.8.6.6.11. Data Structure in I3C Slave x
5.8.6.6.11.1. Transmit Command Data Structure 5.8.6.6.11.2. Response Data Structure
5.8.7. I3C Controller Programming Model x
5.8.7.1. Initializing Common Registers 5.8.7.2. Initializing Master Registers 5.8.7.3. Enabling the Controller 5.8.7.4. Master Mode Operation 5.8.7.5. Initializing Slave Registers 5.8.7.6. Slave Mode Operation 5.8.7.7. DMA Controller Operation
5.8.7.1. Initializing Common Registers x
5.8.7.1.1. Programming Threshold Control Registers 5.8.7.1.2. Programming Interrupt Related Registers
5.8.7.2. Initializing Master Registers x
5.8.7.2.1. Programming DEVICE_ADDR Register 5.8.7.2.2. Programming Timing Registers
5.8.7.4. Master Mode Operation x
5.8.7.4.1. Slave Address Assignment 5.8.7.4.2. Receiving IBI (All types) 5.8.7.4.3. CCC Read/Write Transfers 5.8.7.4.4. Private Read/Write Transfers 5.8.7.4.5. Programming Flow to Prepare the Controller to Switch to Master Mode
5.8.7.4.1. Slave Address Assignment x
5.8.7.4.1.1. ENTDAA Transfer 5.8.7.4.1.2. Issue SETDASA CCC Command
5.8.7.4.3. CCC Read/Write Transfers x
5.8.7.4.3.1. Broadcast CCC Transfer in Master Mode 5.8.7.4.3.2. Directed CCC Transfer in Master Mode
5.8.7.5. Initializing Slave Registers x
5.8.7.5.1. Programming Interrupt Related Registers
5.8.7.6. Slave Mode Operation x
5.8.7.6.1. Private Receive (Master Write) Transfers in Slave Mode 5.8.7.6.2. Private Transmit (Master Read) Transfers in Slave Mode 5.8.7.6.3. Programming Flow for Generating Slave Interrupt Request 5.8.7.6.4. Programming Flow for Generating Master Request 5.8.7.6.5. Programming Flow to Prepare the Controller to Switch to Master Mode 5.8.7.6.6. Command Pipeline and Aggregation of Response Queue Threshold Interrupt 5.8.7.6.7. Error Recovery Flow 5.8.7.6.8. CCC Updated Interrupt Flow 5.8.7.6.9. Flow for Disable and TX/RX/CMD/Response Queue Reset
5.8.7.6.7. Error Recovery Flow x
5.8.7.6.7.1. S0-S5 Error Handling
5.8.9. I3C Controller Design Guidelines and Examples x
5.8.9.1. Guidelines for External SDA and SCL Signals via HPS I/O in the Board Design
5.9. I2C Controller x
5.9.1. I2C Controller Differences Among Intel SoC Device Families 5.9.2. I2C Controller Use Cases 5.9.3. I2C Controller Features 5.9.4. I2C Controller System Integration 5.9.5. I2C Controller Signal Description 5.9.6. I2C Controller Functional Description 5.9.7. I2C Controller Programming Model 5.9.8. I2C Controller Address Map and Register Definitions 5.9.9. I2C Controller Design Guidelines and Examples
5.9.6. I2C Controller Functional Description x
5.9.6.1. Feature Usage 5.9.6.2. Behavior 5.9.6.3. Protocol Details 5.9.6.4. Multiple Master Arbitration 5.9.6.5. Clock Frequency Configuration 5.9.6.6. SDA Hold Time 5.9.6.7. DMA Controller Interface 5.9.6.8. Clocks 5.9.6.9. Resets
5.9.6.2. Behavior x
5.9.6.2.1. START and STOP Generation 5.9.6.2.2. Combined Formats
5.9.6.3. Protocol Details x
5.9.6.3.1. START and STOP Conditions 5.9.6.3.2. Addressing Slave Protocol 5.9.6.3.3. Transmitting and Receiving Protocol 5.9.6.3.4. START BYTE Transfer Protocol
5.9.6.4. Multiple Master Arbitration x
5.9.6.4.1. Clock Synchronization
5.9.6.5. Clock Frequency Configuration x
5.9.6.5.1. Minimum High and Low Counts
5.9.6.5.1. Minimum High and Low Counts x
5.9.6.5.1.1. Calculating High and Low Counts
5.9.6.9. Resets x
5.9.6.9.1. Taking the I2C Controller Out of Reset
5.9.7. I2C Controller Programming Model x
5.9.7.1. Slave Mode Operation 5.9.7.2. Master Mode Operation 5.9.7.3. Disabling the I2C Controller 5.9.7.4. Abort Transfer 5.9.7.5. DMA Controller Operation
5.9.7.1. Slave Mode Operation x
5.9.7.1.1. Initial Configuration 5.9.7.1.2. Slave-Transmitter Operation for a Single Byte 5.9.7.1.3. Slave-Receiver Operation for a Single Byte 5.9.7.1.4. Slave-Transfer Operation for Bulk Transfers 5.9.7.1.5. Slave Programming Model
5.9.7.2. Master Mode Operation x
5.9.7.2.1. Initial Configuration 5.9.7.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update 5.9.7.2.3. Master Transmit and Master Receive 5.9.7.2.4. Master Programming Model
5.9.7.5. DMA Controller Operation x
5.9.7.5.1. Transmit FIFO Underflow 5.9.7.5.2. Transmit Watermark Level 5.9.7.5.3. Transmit FIFO Overflow 5.9.7.5.4. Receive FIFO Overflow 5.9.7.5.5. Receive Watermark Level 5.9.7.5.6. Receive FIFO Underflow
5.9.9. I2C Controller Design Guidelines and Examples x
5.9.9.1. I2C Interface Design Guidelines
5.10. SPI Controller x
5.10.1. SPI Controller Differences Among Intel SoC Device Families 5.10.2. SPI Controller Use Cases 5.10.3. SPI Controller Features 5.10.4. SPI Controller System Integration 5.10.5. SPI Controller Signal Description 5.10.6. SPI Controller Functional Description 5.10.7. SPI Controller Programming Model 5.10.8. SPI Controller Address Map and Register Definitions
5.10.5. SPI Controller Signal Description x
5.10.5.1. Interface to HPS I/O 5.10.5.2. FPGA Routing
5.10.6. SPI Controller Functional Description x
5.10.6.1. Protocol Details and Standards Compliance 5.10.6.2. Overview 5.10.6.3. Serial Bit-Rate Clocks 5.10.6.4. Transmit and Receive FIFO Buffers 5.10.6.5. SPI Interrupts 5.10.6.6. Transfer Modes 5.10.6.7. SPI Master 5.10.6.8. SPI Slave 5.10.6.9. Partner Connection Interfaces 5.10.6.10. DMA Controller Interface 5.10.6.11. Slave Interface 5.10.6.12. Clocks and Resets
5.10.6.3. Serial Bit-Rate Clocks x
5.10.6.3.1. SPI Master Bit-Rate Clock 5.10.6.3.2. SPI Slave Bit-Rate Clock
5.10.6.6. Transfer Modes x
5.10.6.6.1. Transmit and Receive 5.10.6.6.2. Transmit Only 5.10.6.6.3. Receive Only 5.10.6.6.4. EEPROM Read
5.10.6.7. SPI Master x
5.10.6.7.1. Glue Logic for Master Port ss_in_n 5.10.6.7.2. Multi-Master System 5.10.6.7.3. RXD Sample Delay 5.10.6.7.4. Data Transfers 5.10.6.7.5. Master SPI and SSP Serial Transfers 5.10.6.7.6. Master Microwire Serial Transfers
5.10.6.8. SPI Slave x
5.10.6.8.1. Slave SPI and SSP Serial Transfers 5.10.6.8.2. Serial Transfers
5.10.6.9. Partner Connection Interfaces x
5.10.6.9.1. Motorola SPI Protocol 5.10.6.9.2. Texas Instruments Synchronous Serial Protocol (SSP) 5.10.6.9.3. National Semiconductor Microwire Protocol
5.10.6.11. Slave Interface x
5.10.6.11.1. Control and Status Register Access 5.10.6.11.2. Data Register Access
5.10.6.12. Clocks and Resets x
5.10.6.12.1. Clock Gating 5.10.6.12.2. Taking the SPI Controller Out of Reset
5.10.7. SPI Controller Programming Model x
5.10.7.1. Master SPI and SSP Serial Transfers 5.10.7.2. Master Microwire Serial Transfers 5.10.7.3. Slave SPI and SSP Serial Transfers 5.10.7.4. Slave Microwire Serial Transfers 5.10.7.5. Software Control for Slave Selection 5.10.7.6. DMA Controller Operation
5.10.7.5. Software Control for Slave Selection x
5.10.7.5.1. Example: Slave Selection Software Flow for SPI Master 5.10.7.5.2. Example: Slave Selection Software Flow for SPI Slave
5.10.7.6. DMA Controller Operation x
5.10.7.6.1. Transmit FIFO Buffer Underflow 5.10.7.6.2. Transmit FIFO Watermark 5.10.7.6.3. Transmit FIFO Buffer Overflow 5.10.7.6.4. Receive FIFO Buffer Overflow 5.10.7.6.5. Choosing Receive Watermark Level 5.10.7.6.6. Receive FIFO Buffer Underflow
5.10.7.6.2. Transmit FIFO Watermark x
5.10.7.6.2.1. Example 1: Transmit FIFO Watermark Level = 64 5.10.7.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
5.11. Timers x
5.11.1. Timers Differences Among Intel SoC Device Families 5.11.2. Timers Use Cases 5.11.3. Timers Features 5.11.4. Timers System Integration 5.11.5. Timers Functional Description 5.11.6. Timers Programming Model 5.11.7. Timers Address Map and Register Definitions
5.11.5. Timers Functional Description x
5.11.5.1. Clocks 5.11.5.2. Resets 5.11.5.3. Interrupts
5.11.6. Timers Programming Model x
5.11.6.1. Initialization 5.11.6.2. Enabling the Timers 5.11.6.3. Disabling the Timers 5.11.6.4. Loading the Timers Countdown Value 5.11.6.5. Timers Servicing Interrupts
5.11.6.5. Timers Servicing Interrupts x
5.11.6.5.1. Clearing the Interrupt 5.11.6.5.2. Checking the Interrupt Status 5.11.6.5.3. Masking the Interrupt
5.12. Watchdog Timers x
5.12.1. Watchdog Timers Differences Among Intel SoC Device Families 5.12.2. Watchdog Timers Use Cases 5.12.3. Watchdog Timers Features 5.12.4. Watchdog Timers System Integration 5.12.5. Watchdog Timers Functional Description 5.12.6. Watchdog Timers Programming Model 5.12.7. Watchdog Timers Address Map and Register Definitions
5.12.5. Watchdog Timers Functional Description x
5.12.5.1. Watchdog Timers Counter 5.12.5.2. Watchdog Timers Pause Mode 5.12.5.3. Watchdog Timers Clocks 5.12.5.4. Watchdog Timers Resets
5.12.6. Watchdog Timers Programming Model x
5.12.6.1. Setting the Timeout Period Values 5.12.6.2. Selecting the Output Response Mode 5.12.6.3. Enabling and Initially Starting a Watchdog Timers 5.12.6.4. Reloading a Watchdog Counter 5.12.6.5. Pausing a Watchdog Timers 5.12.6.6. Disabling and Stopping a Watchdog Timers 5.12.6.7. Watchdog Timers State Machine
5.13. UART Controller x
5.13.1. UART Controller Differences Among Intel SoC Device Families 5.13.2. UART Controller Use Cases 5.13.3. UART Controller Features 5.13.4. UART Controller System Integration 5.13.5. UART Controller Signal Description 5.13.6. UART Controller Functional Description 5.13.7. UART Controller Address Map and Register Definitions 5.13.8. UART Controller Design Guidelines and Example
5.13.5. UART Controller Signal Description x
5.13.5.1. HPS I/O Pins 5.13.5.2. FPGA Routing
5.13.6. UART Controller Functional Description x
5.13.6.1. FIFO Buffer Support 5.13.6.2. UART Serial Protocol 5.13.6.3. Automatic Flow Control 5.13.6.4. Clocks 5.13.6.5. Resets 5.13.6.6. UART Controller Interrupts 5.13.6.7. UART Controller DMA Controller Operation
5.13.6.7. UART Controller DMA Controller Operation x
5.13.6.7.1. Transmit FIFO Underflow 5.13.6.7.2. Transmit Watermark Level 5.13.6.7.3. Transmit FIFO Overflow 5.13.6.7.4. Receive FIFO Overflow 5.13.6.7.5. Receive Watermark Level 5.13.6.7.6. Receive FIFO Underflow