Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 4/10/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.1. Questa* Intel® FPGA Edition Simulation Steps

  1. Use the following command to change directory to the Mentor Graphics* testbench simulation directory: cd <project directory>/simple_tb/simple_tb/sim/mentor/.
  2. Create a new file and name it my_msim_setup.do . Edit the file with the following content:
    set TOP_LEVEL_NAME simple_tb
    
    ### set QSYS_SIMDIR <script generation output directory>
    set QSYS_SIMDIR ./..
    
    ### source msim_setup.tcl
    source $QSYS_SIMDIR/mentor/msim_setup.tcl
    
    ensure_lib libraries
    ensure_lib libraries/work
    vmap work  libraries/work
    
    ### Compile
    dev_com
    com
    
    vlib work
    
    vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_lwh2f.sv
    vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_h2f_128b.sv
    vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_f2sdram_256b.sv
    vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../my_simple_tb.sv
            
    ### Simulate
    elab_debug
    
    ###add wave *
    
    add wave /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_hps/sundancemesa_hps_inst/lwh2f_bfm_gen/lwh2f_axi4_master_inst/*
    
    add wave /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_hps/sundancemesa_hps_inst/h2f_bfm_gen/h2f_axi4_master_inst/*
    
    add wave /simple_tb/simple_inst/axi4_mm_manager_intf_0/axi4_mm_manager_intf_0/*
    add wave /simple_tb/simple_inst/intel_agilex_5_soc_0/intel_agilex_5_soc_0/sm_mpfe/sundancemesa_mpfe_inst/f2sdram_bfm_gen/f2sdram_axi4_slave_inst/*
    
    ### Run the simulation.
    run -all
    
  3. Set up your developer environment with the proper resources. The Questa* Intel® FPGA Starter Edition is free, however it requires a zero-cost license.
  4. Run the simulation script by being in the Mentor Graphics* testbench simulation directory and executing the simulation command:
    1. cd <project directory>/simple_tb/simple_tb/sim/mentor/
    2. vsim -do my_msim_setup.do
    The following shows the simulation output from this example.
    Figure 54. Example of Simulation Output