Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

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ID 813752
Date 4/10/2025
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 5 Hard Processor System Component 2. Configuring the Agilex™ 5 Hard Processor System Component 3. Simulating the Agilex™ 5 HPS Component 4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, and F2SDRAM) 5. Design Guidelines 6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
1. Introduction to the Agilex™ 5 Hard Processor System Component x
1.1. Release Notes 1.2. Micro Processor Unit 1.3. Application Processor Subsystem 1.4. Peripheral Subsystem 1.5. CoreSight* Debug Components 1.6. Interconnect 1.7. FPGA Bridges 1.8. Introduction to the Agilex™ 5 Hard Processor System Component Revision History
1.1. Release Notes x
1.1.1. HPS IP 7.0.0 1.1.2. HPS IP 6.0.0 1.1.3. HPS IP 5.1.0 1.1.4. HPS IP 4.0.0
2. Configuring the Agilex™ 5 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. HPS-FPGA Interfaces 2.3. SDRAM 2.4. HPS Clocks, Reset, Power 2.5. I/O Delays 2.6. Pin Mux and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2. HPS-FPGA Interfaces x
2.2.1. General 2.2.2. HPS FPGA Bridges 2.2.3. DMA Controller Interface 2.2.4. Interrupts
2.2.1. General x
2.2.1.1. Enable MPU Standby and Event Signals 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB* Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable SWJ-DP JTAG Interface 2.2.1.6. Enable FPGA Cross Trigger Interface 2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.2.2. HPS FPGA Bridges x
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager
2.2.4. Interrupts x
2.2.4.1. FPGA-to-HPS 2.2.4.2. HPS-to-FPGA
2.3. SDRAM x
2.3.1. Configurations for HPS IP 2.3.2. Configurations for HPS EMIF IP 2.3.3. Graphical Connections of HPS to HPS-EMIF 2.3.4. Configuration when using ECC 2.3.5. Configuration of HPS EMIF Calibration Settings 2.3.6. Supported Memory Protocols Among Device Families 2.3.7. IO96 Bank and Lane Usage for HPS EMIF 2.3.8. Quartus Report of I/O Bank Usage 2.3.9. Debugging with the External Memory Interface Debug Toolkit
2.4. HPS Clocks, Reset, Power x
2.4.1. Input Clocks 2.4.2. PLL Clocks 2.4.3. Power and Resets
2.4.1. Input Clocks x
2.4.1.1. External Clocks 2.4.1.2. FPGA-to-HPS Clocks 2.4.1.3. Peripheral FPGA Clocks
2.4.2. PLL Clocks x
2.4.2.1. Main PLL Output 2.4.2.2. Peripheral PLL Output 2.4.2.3. MPU Clocks 2.4.2.4. NOC Clocks 2.4.2.5. Peripheral Clocks 2.4.2.6. HPS-to-FPGA User Clocks
2.4.3. Power and Resets x
2.4.3.1. Power Configurations 2.4.3.2. Reset Signals
2.6. Pin Mux and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. EMAC PTP Interface 2.6.3. HPS I/O Open Drain 2.6.4. HPS I/O Locations
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
2.6.1.1. Auto-Place IP x
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC x
2.6.1.1.1.1. HPS IO Placement Priority
2.6.1.2. Advanced x
2.6.1.2.1. Advanced IP Placement 2.6.1.2.2. Advanced FPGA Placement
3. Simulating the Agilex™ 5 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interface 3.3. FPGA-to-HPS AXI* Subordinate Interface 3.4. FPGA-to-SDRAM AXI* Subordinate Interface 3.5. HPS-to-FPGA AXI* Manager Interface 3.6. Lightweight HPS-to-FPGA AXI* Manager Interface 3.7. Simulating the Agilex™ 5 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSim* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* MX Simulation Steps 3.1.3.4. Riviera-PRO* Simulation Steps 3.1.3.5. Synopsys* VCS* Simulation Steps 3.1.3.6. VSIM Command Line Aliases and Variables
3.2. Clock and Reset Interface x
3.2.1. Clock Interface 3.2.2. Reset Interface
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, and F2SDRAM) x
4.1. Setting up the HPS Component for Simulation 4.2. Generating the HPS Simulation Model in Platform Designer 4.3. Editing the TestBench scripts 4.4. Running the TestBench scripts 4.5. Simulating the Agilex™ 5 HPS Bridges (H2F, LWH2F, and F2SRAM) Revision History
4.3. Editing the TestBench scripts x
4.3.1. my_simple_tb.sv 4.3.2. test_lwh2f.sv 4.3.3. test_h2f_128b.sv 4.3.4. test_f2sdram_256b.sv
4.4. Running the TestBench scripts x
4.4.1. Questa* Intel® FPGA Edition Simulation Steps
5. Design Guidelines x
5.1. HPS System Reset Considerations 5.2. Design Guidelines Revision History
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, and F2SDRAM)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs

2.3.7. IO96 Bank and Lane Usage for HPS EMIF

The following table describes the IO96 Bank and Lane Usage for the various memory protocols when using the HPS-EMIF.
Table 14.  IO96 Bank and Lane Usage for HPS EMIF
Number of signals     12 12 12 12 12 12 12 12
Bank     3A
Sub-Bank     3A_T 3A_B
Bank Lanes   BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0
Protocol Design EMIFs                
DDR4 1x16 1 — — — DQ[1] AC2 AC1 AC0 DQ[0]
1x16_ECC 1 — — DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
1x32 1 — DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1x32_ECC 1 DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
2x32 2 2 — DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
2x32_ECC 22 DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
1x64 — Not Supported
1x64_ECC — Not Supported
DDR5 1x16 1 — — — — AC1 AC0 DQ[0] DQ[1]
1x16_ECC 1 — — — DQ[ECC] AC1 AC0 DQ[0] DQ[1]
2x16 1 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[0] DQ[1]
2x16_ECC — Not Supported
1x32 1 — — DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1x32_ECC 1 — DQ[ECC] DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
2x32 22 — — DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
2x32_ECC 22 — DQ[ECC] DQ[3] DQ[2] AC1 AC0 DQ[0] DQ[1]
1x64 — Not Supported
1x64_ECC — Not Supported

LPDDR4/LPDDR5

 1x16 1 — — — — AC1 AC0 DQ[1] DQ[0]
2x16 1 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
1x32 1 DQ[3] DQ[2] — — AC1 AC0 DQ[1] DQ[0]
2x32 22 DQ[3] DQ[2] — — AC1 AC0 DQ[1] DQ[0]
4x16 22 DQ[1] DQ[0] AC1 AC0 AC1 AC0 DQ[1] DQ[0]
Note: Pins that are not used directly by the HPS-EMIF are available for I/O sharing with other protocols, such as GPIO, MIPI, LVDS SERDES, or PHY Lite, with certain HPS bridge restrictions. These restrictions are described in the tables in the Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) section of the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs.
2 Uses two IOBanks (Banks 3A and 3B)
Level Two Title