Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 4/10/2025
Public

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Document Table of Contents

3.1.3.1. QuestaSim* Simulation Steps

  1. Locate your top-level simulation model, TopLevel.v or TopLevel.vhdl, which you have created.
    1. Locate it at <project directory>/<Platform Designer design name>/sim/.
    2. In this directory, name the file as TopLevel.v or TopLevel.vhdl that was created when you previously click the Generate button.
  2. Locate the msim_setup.tcl script and execute the simulator in the <project directory>/<Platform Designer design name>/sim/mentor/.
  3. Create a new file my_msim_setup.do and write the following content to the file.
    source <path_to>/msim_setup.tcl
    dev_com
    com
    vlog <compilation_options> <design_top_level_vfile> 
    # example: vlog -timescale 1ps/1ps ../TopLevel.v
    
    set TOP_LEVEL_NAME <design_top_level_name> 
    # example: set TOP_LEVEL_NAME TopLevel
    
    set USER_DEFINED_ELAB_OPTIONS <elaboration options> (optional)
    elab
    run -a
    exit -code 0 (optional)
    
    Refer to VSIM Command Line Aliases and Variables for more information about the vsim aliases and variables.
  4. Set up your developer environment with the proper resources. The Questa* Intel® FPGA Starter Edition is free, but it requires a zero-cost license.
  5. Run the simulation script.
    vsim -do my_msim_setup.do
    Since no testbench is added, it only shows that all the HPS IP simulation files were successfully compiled and elaborated using vsim.