Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
8/15/2025
Public
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.3.1. Configurations for HPS IP
2.3.2. Configurations for HPS EMIF IP
2.3.3. Graphical Connections of HPS to HPS-EMIF
2.3.4. Configuration when using ECC
2.3.5. Configuration of HPS EMIF Calibration Settings
2.3.6. Supported Memory Protocols Among Device Families
2.3.7. IO96 Bank and Lane Usage for HPS EMIF
2.3.8. Quartus Report of I/O Bank Usage
2.3.9. Debugging with the External Memory Interface Debug Toolkit
3.1.3.6. VSIM Command Line Aliases and Variables
Command Line Aliases | Description |
---|---|
dev_com | Compile device library files. |
com | Compile the design files in correct order. |
elab | Elaborate top level design. |
elab_debug | Elaborate the top level design with -dbg -O2 option. |
ld | Compile all the design files and elaborate the top level design. |
ld_debug | Compile all the design files and elaborate the top level design with -dbg -O2 option. |
Variables | Description |
---|---|
TOP_LEVEL_NAME | Top level module name. |
QSYS_SIMDIR | Platform Designer base simulation directory. |
QUARTUS_INSTALL_DIR | Quartus installation directory. |
USER_DEFINED_COMPILE_OPTIONS | User-defined compile options, added to com/dev_com aliases. |
USER_DEFINED_VHDL_COMPILE_OPTIONS | User-defined vhdl compile options, added to com/dev_com aliases. |
USER_DEFINED_VERILOG_COMPILE_OPTIONS | User-defined verilog compile options, added to com/dev_com aliases. |
USER_DEFINED_ELAB_OPTIONS | User-defined elaboration options, added to elab/elab_debug aliases. |