Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/15/2025
Public
Document Table of Contents

3.1.3.6. VSIM Command Line Aliases and Variables

Table 18.  List of Command Line Aliases
Command Line Aliases Description
dev_com Compile device library files.
com Compile the design files in correct order.
elab Elaborate top level design.
elab_debug Elaborate the top level design with -dbg -O2 option.
ld Compile all the design files and elaborate the top level design.
ld_debug Compile all the design files and elaborate the top level design with -dbg -O2 option.
Table 19.  List of Variables
Variables Description
TOP_LEVEL_NAME Top level module name.
QSYS_SIMDIR Platform Designer base simulation directory.
QUARTUS_INSTALL_DIR Quartus installation directory.
USER_DEFINED_COMPILE_OPTIONS User-defined compile options, added to com/dev_com aliases.
USER_DEFINED_VHDL_COMPILE_OPTIONS User-defined vhdl compile options, added to com/dev_com aliases.
USER_DEFINED_VERILOG_COMPILE_OPTIONS User-defined verilog compile options, added to com/dev_com aliases.
USER_DEFINED_ELAB_OPTIONS User-defined elaboration options, added to elab/elab_debug aliases.