Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/15/2025
Public
Document Table of Contents

6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs

Date Quartus® Prime version Changes
2025.08.15 25.1.1
  • Added HPS IP 9.0.0 entry in the Release Notes section.
  • Added note about REQ and WED settings in the Configuration of HPS EMIF Calibration Settings.
  • Added note about using f2h_free_clk as input clock in the FPGA-to-HPS Clocks topic.
  • Renamed to Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H) section to include information on F2H ACE5-Lite Bus Functional Model (BFM).
  • Added test_f2h.sv with instructions to set up F2H simulation (ACE5-Lite).
  • Updated the testbench script in the following sections:
    • my_simple_tb.sv
    • test_h2f.sv
    • test_f2sdram.sv
    • test_f2h.sv
    • Questa* Intel® FPGA Edition Simulation Steps
2025.04.10 25.1
  • Added HPS IP 7.0.0 entry in the Release Notes section.
  • Added Debugging with the External Memory Interface Debug Toolkit section.
  • Added Simulating the Agilex 5 HPS bridges (H2F, LWH2F, and F2SDRAM) section.
  • Added Configuration of HPS EMIF Calibration Settings section.
  • Added note about I/O sharing on HPS EMIF in the following topics:
    • FPGA to HPS Subordinate
    • FPGA to SDRAM Subordinate
    • IO96 Bank and Lane Usage for HPS EMIF
    • Quartus Report of I/O Usage
  • Added note about connecting the interfaces properly to avoid errors in Quartus compilation in the following topics:
    • HPS FPGA Bridges
    • FPGA to HPS Subordinate
    • FPGA to SDRAM Subordinate
    • HPS to FPGA Manager
    • Lightweight HPS to FPGA Manager
2025.02.26 24.3.1
  • Added HPS IP 6.0.0 entry in the Release Notes section.
  • Updated information about configuring CPU cores for power consumption of the HPS in Power Configurations.
  • Updated simulation steps about QuestaSim* , Cadence® Xcelium* , Synopsys* VCS* MX, and Riviera-PRO* AXI* Interfaces in the following topics:
    • Setting Up the HPS Component for Simulation
    • Generating the HPS Simulation Model in Platform Designer
    • RTL Simulation Setup Scripts
  • Added VSIM Command Line Aliases and Variables topic.
  • Removed Running the Simulation of the Design Examples section.
  • Updated the FPGA to HPS Subordinate and FPGA to SDRAM Subordinate topics with information about Enable System MMU Ports option.
  • Updated note and example about viewing the address space through the F2SDRAM interface in FPGA to SDRAM Subordinate topic.
  • Updated the following figures:
    • Platform Designer HPS-FPGA Bridges Sub-window
    • Platform Designer Input Clocks Sub-tab
    • Platform Designer - Generate HDL button
    • Platform Designer - Select Simulators to Generate
2024.11.25 24.3
  • Added Release Notes section to describe the HPS IP changes.
  • Updated SDRAM topic with the configurations for HPS EMIF IP.
  • Added information on F2H Interface Specifications in HPS FPGA Bridges.
  • Updated Interrupt's FPGA-to-HPS conduit in FPGA-to-HPS.
  • Added information about ACES5-Lite Cache Coherency Translator in FPGA to HPS Subordinate topic.
  • Added note about reinstating the IPs when prompted to upgrade the HPS IP and On-Chip RAM IP in HPS-to-FPGA Bridge (H2F), Lightweight HPS-to-FPGA (LWH2F), and FPGA-to-SDRAM Bridge (F2SDRAM) topics.
  • Added note about the support of F2H simulation in FPGA-to-HPS Bridge (F2H) topic.
  • Removed the HPS EMIF Platform Designer Example Designs section.
  • Updated the following figures;
    • Platform Designer HPS-FPGA Bridges Sub-window
    • Platform Designer: Pin Mux and Peripherals: Auto-Place IP GUI
2024.08.09 24.2
  • Added HPS EMIF Platform Designer Example Designs section.
  • Updated signal names in Table: Enable GP Signals.
  • Updated Figure: Platform Designer MPU Clocks Sub-window.
2024.05.02 24.1 Initial release.