Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

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ID 813752
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 5 Hard Processor System Component 2. Configuring the Agilex™ 5 Hard Processor System Component 3. Simulating the Agilex™ 5 HPS Component 4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H) 5. Design Guidelines 6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
1. Introduction to the Agilex™ 5 Hard Processor System Component x
1.1. Release Notes 1.2. Micro Processor Unit 1.3. Application Processor Subsystem 1.4. Peripheral Subsystem 1.5. CoreSight* Debug Components 1.6. Interconnect 1.7. FPGA Bridges 1.8. Introduction to the Agilex™ 5 Hard Processor System Component Revision History
1.1. Release Notes x
1.1.1. HPS IP 9.0.0 1.1.2. HPS IP 7.0.0 1.1.3. HPS IP 6.0.0 1.1.4. HPS IP 5.1.0 1.1.5. HPS IP 4.0.0
2. Configuring the Agilex™ 5 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. HPS-FPGA Interfaces 2.3. SDRAM 2.4. HPS Clocks, Reset, Power 2.5. I/O Delays 2.6. Pin Mux and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2. HPS-FPGA Interfaces x
2.2.1. General 2.2.2. HPS FPGA Bridges 2.2.3. DMA Controller Interface 2.2.4. Interrupts
2.2.1. General x
2.2.1.1. Enable MPU Standby and Event Signals 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB* Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable SWJ-DP JTAG Interface 2.2.1.6. Enable FPGA Cross Trigger Interface 2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.2.2. HPS FPGA Bridges x
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager
2.2.4. Interrupts x
2.2.4.1. FPGA-to-HPS 2.2.4.2. HPS-to-FPGA
2.3. SDRAM x
2.3.1. Configurations for HPS IP 2.3.2. Configurations for HPS EMIF IP 2.3.3. Graphical Connections of HPS to HPS-EMIF 2.3.4. Configuration when using ECC 2.3.5. Configuration of HPS EMIF Calibration Settings 2.3.6. Supported Memory Protocols Among Device Families 2.3.7. IO96 Bank and Lane Usage for HPS EMIF 2.3.8. Quartus Report of I/O Bank Usage 2.3.9. Debugging with the External Memory Interface Debug Toolkit
2.4. HPS Clocks, Reset, Power x
2.4.1. Input Clocks 2.4.2. PLL Clocks 2.4.3. Power and Resets
2.4.1. Input Clocks x
2.4.1.1. External Clocks 2.4.1.2. FPGA-to-HPS Clocks 2.4.1.3. Peripheral FPGA Clocks
2.4.2. PLL Clocks x
2.4.2.1. Main PLL Output 2.4.2.2. Peripheral PLL Output 2.4.2.3. MPU Clocks 2.4.2.4. NOC Clocks 2.4.2.5. Peripheral Clocks 2.4.2.6. HPS-to-FPGA User Clocks
2.4.3. Power and Resets x
2.4.3.1. Power Configurations 2.4.3.2. Reset Signals
2.6. Pin Mux and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. EMAC PTP Interface 2.6.3. HPS I/O Open Drain 2.6.4. HPS I/O Locations
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
2.6.1.1. Auto-Place IP x
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC x
2.6.1.1.1.1. HPS IO Placement Priority
2.6.1.2. Advanced x
2.6.1.2.1. Advanced IP Placement 2.6.1.2.2. Advanced FPGA Placement
3. Simulating the Agilex™ 5 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interface 3.3. FPGA-to-HPS AXI* Subordinate Interface 3.4. FPGA-to-SDRAM AXI* Subordinate Interface 3.5. HPS-to-FPGA AXI* Manager Interface 3.6. Lightweight HPS-to-FPGA AXI* Manager Interface 3.7. Simulating the Agilex™ 5 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSim* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* MX Simulation Steps 3.1.3.4. Riviera-PRO* Simulation Steps 3.1.3.5. Synopsys* VCS* Simulation Steps 3.1.3.6. VSIM Command Line Aliases and Variables
3.2. Clock and Reset Interface x
3.2.1. Clock Interface 3.2.2. Reset Interface
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H) x
4.1. Setting up the HPS Component for Simulation 4.2. Generating the HPS Simulation Model in Platform Designer 4.3. Editing the TestBench scripts 4.4. Running the TestBench scripts 4.5. Simulating the Agilex™ 5 HPS Bridges (H2F, LWH2F, F2SRAM, F2H) Revision History
4.3. Editing the TestBench scripts x
4.3.1. my_simple_tb.sv 4.3.2. test_lwh2f.sv 4.3.3. test_h2f.sv 4.3.4. test_f2sdram.sv 4.3.5. test_f2h.sv
4.4. Running the TestBench scripts x
4.4.1. Questa* Intel® FPGA Edition Simulation Steps
5. Design Guidelines x
5.1. HPS System Reset Considerations 5.2. Design Guidelines Revision History
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs

6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs

Date Quartus® Prime version Changes
2025.08.15 25.1.1
  • Added HPS IP 9.0.0 entry in the Release Notes section.
  • Added note about REQ and WED settings in the Configuration of HPS EMIF Calibration Settings.
  • Added note about using f2h_free_clk as input clock in the FPGA-to-HPS Clocks topic.
  • Renamed to Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, F2SDRAM, F2H) section to include information on F2H ACE5-Lite Bus Functional Model (BFM).
  • Added test_f2h.sv with instructions to set up F2H simulation (ACE5-Lite).
  • Updated the testbench script in the following sections:
    • my_simple_tb.sv
    • test_h2f.sv
    • test_f2sdram.sv
    • test_f2h.sv
    • Questa* Intel® FPGA Edition Simulation Steps
2025.04.10 25.1
  • Added HPS IP 7.0.0 entry in the Release Notes section.
  • Added Debugging with the External Memory Interface Debug Toolkit section.
  • Added Simulating the Agilex 5 HPS bridges (H2F, LWH2F, and F2SDRAM) section.
  • Added Configuration of HPS EMIF Calibration Settings section.
  • Added note about I/O sharing on HPS EMIF in the following topics:
    • FPGA to HPS Subordinate
    • FPGA to SDRAM Subordinate
    • IO96 Bank and Lane Usage for HPS EMIF
    • Quartus Report of I/O Usage
  • Added note about connecting the interfaces properly to avoid errors in Quartus compilation in the following topics:
    • HPS FPGA Bridges
    • FPGA to HPS Subordinate
    • FPGA to SDRAM Subordinate
    • HPS to FPGA Manager
    • Lightweight HPS to FPGA Manager
2025.02.26 24.3.1
  • Added HPS IP 6.0.0 entry in the Release Notes section.
  • Updated information about configuring CPU cores for power consumption of the HPS in Power Configurations.
  • Updated simulation steps about QuestaSim* , Cadence® Xcelium* , Synopsys* VCS* MX, and Riviera-PRO* AXI* Interfaces in the following topics:
    • Setting Up the HPS Component for Simulation
    • Generating the HPS Simulation Model in Platform Designer
    • RTL Simulation Setup Scripts
  • Added VSIM Command Line Aliases and Variables topic.
  • Removed Running the Simulation of the Design Examples section.
  • Updated the FPGA to HPS Subordinate and FPGA to SDRAM Subordinate topics with information about Enable System MMU Ports option.
  • Updated note and example about viewing the address space through the F2SDRAM interface in FPGA to SDRAM Subordinate topic.
  • Updated the following figures:
    • Platform Designer HPS-FPGA Bridges Sub-window
    • Platform Designer Input Clocks Sub-tab
    • Platform Designer - Generate HDL button
    • Platform Designer - Select Simulators to Generate
2024.11.25 24.3
  • Added Release Notes section to describe the HPS IP changes.
  • Updated SDRAM topic with the configurations for HPS EMIF IP.
  • Added information on F2H Interface Specifications in HPS FPGA Bridges.
  • Updated Interrupt's FPGA-to-HPS conduit in FPGA-to-HPS.
  • Added information about ACES5-Lite Cache Coherency Translator in FPGA to HPS Subordinate topic.
  • Added note about reinstating the IPs when prompted to upgrade the HPS IP and On-Chip RAM IP in HPS-to-FPGA Bridge (H2F), Lightweight HPS-to-FPGA (LWH2F), and FPGA-to-SDRAM Bridge (F2SDRAM) topics.
  • Added note about the support of F2H simulation in FPGA-to-HPS Bridge (F2H) topic.
  • Removed the HPS EMIF Platform Designer Example Designs section.
  • Updated the following figures;
    • Platform Designer HPS-FPGA Bridges Sub-window
    • Platform Designer: Pin Mux and Peripherals: Auto-Place IP GUI
2024.08.09 24.2
  • Added HPS EMIF Platform Designer Example Designs section.
  • Updated signal names in Table: Enable GP Signals.
  • Updated Figure: Platform Designer MPU Clocks Sub-window.
2024.05.02 24.1 Initial release.
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