Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/15/2025
Public
Document Table of Contents

3.3. FPGA-to-HPS AXI* Subordinate Interface

The FPGA-to-HPS AXI* subordinate interface, fpga2hps, is connected to a AXI* Manager BFM for simulation. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to the fpga2hps_clock clock and the reset input is connected to fpga2hps_reset.

Table 24.  Configuration of FPGA-to-HPS AXI* Subordinate BFM
Parameter Value
AXI* Address Width 20-40
AXI* Read Data Width 256
AXI* Write Data Width 256
AXI* ID Width 5

You control and monitor the AXI* 4 subordinate BFM by using the BFM API.